Unverified Commit d958edb9 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge tag 'dt-fixes-for-palmer-6.0-rc4' of... 

Merge tag 'dt-fixes-for-palmer-6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git

 into fixes

Microchip RISC-V devicetree fixes for 6.0-rc4 (or later)

A fix for the warnings introduced in rc3 as part of fixing the console
spam from the L2's isr.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>

* tag 'dt-fixes-for-palmer-6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git:
  riscv: dts: microchip: use an mpfs specific l2 compatible
  dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible
parents 1709c70c 0dec364f

Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml

+49 −30
Original line number Diff line number Diff line
@@ -17,9 +17,6 @@ description: 
  acts as directory-based coherency manager.

  All the properties in ePAPR/DeviceTree specification applies for this platform.



allOf:

  - $ref: /schemas/cache-controller.yaml#



select:

  properties:

    compatible:
@@ -33,11 +30,16 @@ select: 


properties:

  compatible:

    items:

    oneOf:

      - items:

          - enum:

              - sifive,fu540-c000-ccache

              - sifive,fu740-c000-ccache

          - const: cache

      - items:

          - const: microchip,mpfs-ccache

          - const: sifive,fu540-c000-ccache

          - const: cache



  cache-block-size:

    const: 64
@@ -72,30 +74,47 @@ properties: 
      The reference to the reserved-memory for the L2 Loosely Integrated Memory region.

      The reserved memory node should be defined as per the bindings in reserved-memory.txt.



if:

allOf:

  - $ref: /schemas/cache-controller.yaml#



  - if:

      properties:

        compatible:

          contains:

        const: sifive,fu540-c000-ccache

            enum:

              - sifive,fu740-c000-ccache

              - microchip,mpfs-ccache



    then:

      properties:

        interrupts:

          description: |

        Must contain entries for DirError, DataError and DataFail signals.

      maxItems: 3

    cache-sets:

      const: 1024

            Must contain entries for DirError, DataError, DataFail, DirFail signals.

          minItems: 4



    else:

      properties:

        interrupts:

          description: |

        Must contain entries for DirError, DataError, DataFail, DirFail signals.

      minItems: 4

            Must contain entries for DirError, DataError and DataFail signals.

          maxItems: 3



  - if:

      properties:

        compatible:

          contains:

            const: sifive,fu740-c000-ccache



    then:

      properties:

        cache-sets:

          const: 2048



    else:

      properties:

        cache-sets:

          const: 1024



additionalProperties: false



required:

arch/riscv/boot/dts/microchip/mpfs.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -185,7 +185,7 @@ 
		ranges;



		cctrllr: cache-controller@2010000 {

			compatible = "sifive,fu540-c000-ccache", "cache";

			compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";

			reg = <0x0 0x2010000 0x0 0x1000>;

			cache-block-size = <64>;

			cache-level = <2>;