Commit d9426c3d authored by Le Ma's avatar Le Ma Committed by Alex Deucher
Browse files

drm/amdgpu: add bitmask to iterate vmhubs 



As the layout of VMHUB definition has been changed to cover multiple
XCD/AID case, the original num_vmhubs is not appropriate to do vmhub
iteration any more.

Drop num_vmhubs and introduce vmhubs_mask instead.

v2: switch to the new VMHUB layout
v3: use DECLARE_BITMAP to define vmhubs_mask

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b35ce49a

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −1
Original line number Diff line number Diff line
@@ -829,7 +829,7 @@ struct amdgpu_device { 
	dma_addr_t			dummy_page_addr;

	struct amdgpu_vm_manager	vm_manager;

	struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];

	unsigned			num_vmhubs;

	DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);



	/* memory management */

	struct amdgpu_mman		mman;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+1 −1
Original line number Diff line number Diff line
@@ -733,7 +733,7 @@ int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev, 
	if (adev->family == AMDGPU_FAMILY_AI) {

		int i;



		for (i = 0; i < adev->num_vmhubs; i++)

		for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)

			amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);

	} else {

		amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c

+2 −2
Original line number Diff line number Diff line
@@ -182,7 +182,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 
	}

	mb();

	amdgpu_device_flush_hdp(adev, NULL);

	for (i = 0; i < adev->num_vmhubs; i++)

	for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)

		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);



	drm_dev_exit(idx);
@@ -264,7 +264,7 @@ void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev) 


	mb();

	amdgpu_device_flush_hdp(adev, NULL);

	for (i = 0; i < adev->num_vmhubs; i++)

	for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)

		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);

}

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

+3 −2
Original line number Diff line number Diff line
@@ -460,7 +460,7 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 
				&queried_pasid);

		if (ret	&& queried_pasid == pasid) {

			if (all_hub) {

				for (i = 0; i < adev->num_vmhubs; i++)

				for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)

					gmc_v10_0_flush_gpu_tlb(adev, vmid,

							i, flush_type);

			} else {
@@ -928,7 +928,8 @@ static int gmc_v10_0_sw_init(void *handle) 
	case IP_VERSION(10, 3, 6):

	case IP_VERSION(10, 3, 3):

	case IP_VERSION(10, 3, 7):

		adev->num_vmhubs = 2;

		set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);

		set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);

		/*

		 * To fulfill 4-level page support,

		 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

+3 −2
Original line number Diff line number Diff line
@@ -364,7 +364,7 @@ static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 
				&queried_pasid);

		if (ret	&& queried_pasid == pasid) {

			if (all_hub) {

				for (i = 0; i < adev->num_vmhubs; i++)

				for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)

					gmc_v11_0_flush_gpu_tlb(adev, vmid,

							i, flush_type);

			} else {
@@ -779,7 +779,8 @@ static int gmc_v11_0_sw_init(void *handle) 
	case IP_VERSION(11, 0, 2):

	case IP_VERSION(11, 0, 3):

	case IP_VERSION(11, 0, 4):

		adev->num_vmhubs = 2;

		set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);

		set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);

		/*

		 * To fulfill 4-level page support,

		 * vm size is 256TB (48bit), maximum size,