Commit d92df6fb authored by Biju Das's avatar Biju Das Committed by Lee Jones
Browse files

mfd: rz-mtu3: Replace raw_spin_lock->spin_lock() 



As per kernel documentation, use raw_spinlock_t only in real critical core
code, low-level interrupt handling, and places where disabling preemption
or interrupts is required. Here the lock is for concurrent register access
from different drivers, hence spin_lock() is sufficient.

Reported-by: default avatarPavel Machek <pavel@denx.de>
Closes: https://lore.kernel.org/all/ZIL%2FitcJvV5s3Bnf@duo.ucw.cz/


Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarPavel Machek <pavel@denx.de>
Link: https://lore.kernel.org/r/20230815073445.9579-3-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarLee Jones <lee@kernel.org>
parent a160d128

drivers/mfd/rz-mtu3.c

+8 −8
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
struct rz_mtu3_priv {

	void __iomem *mmio;

	struct reset_control *rstc;

	raw_spinlock_t lock;

	spinlock_t lock;

};



/******* MTU3 registers (original offset is +0x1200) *******/
@@ -176,11 +176,11 @@ void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, u16 offset, 
	struct rz_mtu3_priv *priv = mtu->priv_data;

	unsigned long tmdr, flags;



	raw_spin_lock_irqsave(&priv->lock, flags);

	spin_lock_irqsave(&priv->lock, flags);

	tmdr = rz_mtu3_shared_reg_read(ch, offset);

	__assign_bit(pos, &tmdr, !!val);

	rz_mtu3_shared_reg_write(ch, offset, tmdr);

	raw_spin_unlock_irqrestore(&priv->lock, flags);

	spin_unlock_irqrestore(&priv->lock, flags);

}

EXPORT_SYMBOL_GPL(rz_mtu3_shared_reg_update_bit);
@@ -256,13 +256,13 @@ static void rz_mtu3_start_stop_ch(struct rz_mtu3_channel *ch, bool start) 
	bitpos = rz_mtu3_get_tstr_bit_pos(ch);



	/* start stop register shared by multiple timer channels */

	raw_spin_lock_irqsave(&priv->lock, flags);

	spin_lock_irqsave(&priv->lock, flags);



	tstr = rz_mtu3_shared_reg_read(ch, offset);

	__assign_bit(bitpos, &tstr, start);

	rz_mtu3_shared_reg_write(ch, offset, tstr);



	raw_spin_unlock_irqrestore(&priv->lock, flags);

	spin_unlock_irqrestore(&priv->lock, flags);

}



bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch)
@@ -277,9 +277,9 @@ bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch) 
	bitpos = rz_mtu3_get_tstr_bit_pos(ch);



	/* start stop register shared by multiple timer channels */

	raw_spin_lock_irqsave(&priv->lock, flags);

	spin_lock_irqsave(&priv->lock, flags);

	tstr = rz_mtu3_shared_reg_read(ch, offset);

	raw_spin_unlock_irqrestore(&priv->lock, flags);

	spin_unlock_irqrestore(&priv->lock, flags);



	return tstr & BIT(bitpos);

}
@@ -349,7 +349,7 @@ static int rz_mtu3_probe(struct platform_device *pdev) 
		return PTR_ERR(ddata->clk);



	reset_control_deassert(priv->rstc);

	raw_spin_lock_init(&priv->lock);

	spin_lock_init(&priv->lock);

	platform_set_drvdata(pdev, ddata);



	for (i = 0; i < RZ_MTU_NUM_CHANNELS; i++) {