Commit d91e775e authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Lorenzo Pieralisi
Browse files

dt-bindings: PCI: ti,am65: Fix "ti,syscon-pcie-id"/"ti,syscon-pcie-mode" to take argument 

Fix binding documentation of "ti,syscon-pcie-id" and "ti,syscon-pcie-mode"
to take phandle with argument. The argument is the register offset within
"syscon" used to configure PCIe controller. Similar change for j721e is
discussed in [1]

[1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com

Link: https://lore.kernel.org/r/20211126083119.16570-2-kishon@ti.com


Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
parent fa55b7dc

Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml

+6 −2
Original line number Diff line number Diff line
@@ -32,8 +32,12 @@ properties: 
    maxItems: 1



  ti,syscon-pcie-mode:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: Phandle to the SYSCON entry

          - description: pcie_ctrl register offset within SYSCON

    description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.

    $ref: /schemas/types.yaml#/definitions/phandle



  interrupts:

    minItems: 1
@@ -65,7 +69,7 @@ examples: 
               <0x5506000 0x1000>;

        reg-names = "app", "dbics", "addr_space", "atu";

        power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;

        ti,syscon-pcie-mode = <&pcie0_mode>;

        ti,syscon-pcie-mode = <&scm_conf 0x4060>;

        num-ib-windows = <16>;

        num-ob-windows = <16>;

        max-link-speed = <2>;

Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml

+12 −4
Original line number Diff line number Diff line
@@ -33,12 +33,20 @@ properties: 
    maxItems: 1



  ti,syscon-pcie-id:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: Phandle to the SYSCON entry

          - description: pcie_device_id register offset within SYSCON

    description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID

    $ref: /schemas/types.yaml#/definitions/phandle



  ti,syscon-pcie-mode:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: Phandle to the SYSCON entry

          - description: pcie_ctrl register offset within SYSCON

    description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.

    $ref: /schemas/types.yaml#/definitions/phandle



  msi-map: true
@@ -84,8 +92,8 @@ examples: 
        #size-cells = <2>;

        ranges = <0x81000000 0 0          0x10020000 0 0x00010000>,

                 <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;

        ti,syscon-pcie-id = <&pcie_devid>;

        ti,syscon-pcie-mode = <&pcie0_mode>;

        ti,syscon-pcie-id = <&scm_conf 0x0210>;

        ti,syscon-pcie-mode = <&scm_conf 0x4060>;

        bus-range = <0x0 0xff>;

        num-viewport = <16>;

        max-link-speed = <2>;