Commit d8e0b16d authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: tag swSMU code layers 



Per designs, the swSMU code is separated into four layers. And the typical
calling flow should be like: amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c
-> smu_cmn.c. Compile errors will come out for any violations. This can
help to prevent cross callings(e.g. amdgpu_smu.c -> ${asic}_ppt.c ->
amdgpu_smu.c -> ${asic}_ppt.c) which were common in our code.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 70475931

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+2 −2
Original line number Diff line number Diff line
@@ -20,14 +20,14 @@ 
 * OTHER DEALINGS IN THE SOFTWARE.

 */



#define SWSMU_CODE_LAYER_L1



#include <linux/firmware.h>

#include <linux/pci.h>



#include "amdgpu.h"

#include "amdgpu_smu.h"

#include "smu_internal.h"

#include "smu_v11_0.h"

#include "smu_v12_0.h"

#include "atom.h"

#include "arcturus_ppt.h"

#include "navi10_ppt.h"

drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

+2 −1
Original line number Diff line number Diff line
@@ -21,10 +21,11 @@ 
 *

 */



#define SWSMU_CODE_LAYER_L2



#include <linux/firmware.h>

#include "amdgpu.h"

#include "amdgpu_smu.h"

#include "smu_internal.h"

#include "atomfirmware.h"

#include "amdgpu_atomfirmware.h"

#include "amdgpu_atombios.h"

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

+2 −0
Original line number Diff line number Diff line
@@ -653,6 +653,7 @@ enum smu_cmn2asic_mapping_type { 
#define WORKLOAD_MAP(profile, workload) \

	[profile] = {1, (workload)}



#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)

int smu_load_microcode(struct smu_context *smu);



int smu_check_fw_status(struct smu_context *smu);
@@ -790,3 +791,4 @@ int smu_get_dpm_clock_table(struct smu_context *smu, 
int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);



#endif

#endif

drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h

+3 −0
Original line number Diff line number Diff line
@@ -134,6 +134,8 @@ enum smu_v11_0_baco_seq { 
	BACO_SEQ_COUNT,

};



#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)



int smu_v11_0_init_microcode(struct smu_context *smu);



void smu_v11_0_fini_microcode(struct smu_context *smu);
@@ -263,3 +265,4 @@ int smu_v11_0_get_dpm_level_range(struct smu_context *smu, 
				  uint32_t *max_value);



#endif

#endif

drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h

+3 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ 
#define MP1_Public			0x03b00000

#define MP1_SRAM			0x03c00004



#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)



int smu_v12_0_check_fw_status(struct smu_context *smu);



int smu_v12_0_check_fw_version(struct smu_context *smu);
@@ -59,3 +61,4 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_ 
int smu_v12_0_set_driver_table_location(struct smu_context *smu);



#endif

#endif