Commit d8dbf923 authored by Lee Jones's avatar Lee Jones Committed by Stephen Boyd
Browse files

clk: ti: dpll44xx: Fix some potential doc-rot 



Fixes the following W=1 kernel build warning(s):

 drivers/clk/ti/dpll44xx.c:114: warning: Function parameter or member 'hw' not described in 'omap4_dpll_regm4xen_recalc'
 drivers/clk/ti/dpll44xx.c:114: warning: Function parameter or member 'parent_rate' not described in 'omap4_dpll_regm4xen_recalc'
 drivers/clk/ti/dpll44xx.c:114: warning: Excess function parameter 'clk' description in 'omap4_dpll_regm4xen_recalc'
 drivers/clk/ti/dpll44xx.c:150: warning: Function parameter or member 'hw' not described in 'omap4_dpll_regm4xen_round_rate'
 drivers/clk/ti/dpll44xx.c:150: warning: Function parameter or member 'parent_rate' not described in 'omap4_dpll_regm4xen_round_rate'
 drivers/clk/ti/dpll44xx.c:150: warning: Excess function parameter 'clk' description in 'omap4_dpll_regm4xen_round_rate'

Cc: Tero Kristo <kristo@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-omap@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20210126124540.3320214-11-lee.jones@linaro.org


Reviewed-by: default avatarTero Kristo <kristo@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent b565eb81

drivers/clk/ti/dpll44xx.c

+4 −2
Original line number Diff line number Diff line
@@ -102,7 +102,8 @@ static void omap4_dpll_lpmode_recalc(struct dpll_data *dd) 


/**

 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit

 * @clk: struct clk * of the DPLL to compute the rate for

 * @hw: pointer to the clock to compute the rate for

 * @parent_rate: clock rate of the DPLL parent

 *

 * Compute the output rate for the OMAP4 DPLL represented by @clk.

 * Takes the REGM4XEN bit into consideration, which is needed for the
@@ -134,8 +135,9 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 


/**

 * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit

 * @clk: struct clk * of the DPLL to round a rate for

 * @hw: struct hw_clk containing the struct clk * of the DPLL to round a rate for

 * @target_rate: the desired rate of the DPLL

 * @parent_rate: clock rate of the DPLL parent

 *

 * Compute the rate that would be programmed into the DPLL hardware

 * for @clk if set_rate() were to be provided with the rate