Commit d8d12312 authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915/gvt: replace IS_GEN and friends with GRAPHICS_VER 



This was done by the following semantic patch:

	@@ expression i915; @@
	- INTEL_GEN(i915)
	+ GRAPHICS_VER(i915)

	@@ expression i915; expression E; @@
	- INTEL_GEN(i915) >= E
	+ GRAPHICS_VER(i915) >= E

	@@ expression dev_priv; expression E; @@
	- !IS_GEN(dev_priv, E)
	+ GRAPHICS_VER(dev_priv) != E

	@@ expression dev_priv; expression E; @@
	- IS_GEN(dev_priv, E)
	+ GRAPHICS_VER(dev_priv) == E

	@@
	expression dev_priv;
	expression from, until;
	@@
	- IS_GEN_RANGE(dev_priv, from, until)
	+ IS_GRAPHICS_VER(dev_priv, from, until)

	@def@
	expression E;
	identifier id =~ "^gen$";
	@@
	- id = GRAPHICS_VER(E)
	+ ver = GRAPHICS_VER(E)

	@@
	identifier def.id;
	@@
	- id
	+ ver

It also takes care of renaming the variable we assign to GRAPHICS_VER()
so to use "ver" rather than "gen".

Cc: intel-gvt-dev@lists.freedesktop.org
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210603165428.3625495-5-lucas.demarchi@intel.com
parent e2bebb92

drivers/gpu/drm/i915/gvt/cmd_parser.c

+4 −4
Original line number Diff line number Diff line
@@ -1006,7 +1006,7 @@ static int cmd_reg_handler(struct parser_exec_state *s, 
	 * update reg values in it into vregs, so LRIs in workload with

	 * inhibit context will restore with correct values

	 */

	if (IS_GEN(s->engine->i915, 9) &&

	if (GRAPHICS_VER(s->engine->i915) == 9 &&

	    intel_gvt_mmio_is_sr_in_ctx(gvt, offset) &&

	    !strncmp(cmd, "lri", 3)) {

		intel_gvt_hypervisor_read_gpa(s->vgpu,
@@ -1390,7 +1390,7 @@ static int gen8_check_mi_display_flip(struct parser_exec_state *s, 
	if (!info->async_flip)

		return 0;



	if (INTEL_GEN(s->engine->i915) >= 9) {

	if (GRAPHICS_VER(s->engine->i915) >= 9) {

		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);

		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &

				GENMASK(12, 10)) >> 10;
@@ -1418,7 +1418,7 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 


	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),

		      info->surf_val << 12);

	if (INTEL_GEN(dev_priv) >= 9) {

	if (GRAPHICS_VER(dev_priv) >= 9) {

		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),

			      info->stride_val);

		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
@@ -1446,7 +1446,7 @@ static int decode_mi_display_flip(struct parser_exec_state *s, 
{

	if (IS_BROADWELL(s->engine->i915))

		return gen8_decode_mi_display_flip(s, info);

	if (INTEL_GEN(s->engine->i915) >= 9)

	if (GRAPHICS_VER(s->engine->i915) >= 9)

		return skl_decode_mi_display_flip(s, info);



	return -ENODEV;

drivers/gpu/drm/i915/gvt/dmabuf.c

+1 −1
Original line number Diff line number Diff line
@@ -223,7 +223,7 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, 


	obj->read_domains = I915_GEM_DOMAIN_GTT;

	obj->write_domain = 0;

	if (INTEL_GEN(dev_priv) >= 9) {

	if (GRAPHICS_VER(dev_priv) >= 9) {

		unsigned int tiling_mode = 0;

		unsigned int stride = 0;

drivers/gpu/drm/i915/gvt/fb_decoder.c

+5 −5
Original line number Diff line number Diff line
@@ -151,7 +151,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe, 
	u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;

	u32 stride = stride_reg;



	if (INTEL_GEN(dev_priv) >= 9) {

	if (GRAPHICS_VER(dev_priv) >= 9) {

		switch (tiled) {

		case PLANE_CTL_TILED_LINEAR:

			stride = stride_reg * 64;
@@ -215,7 +215,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 
	if (!plane->enabled)

		return -ENODEV;



	if (INTEL_GEN(dev_priv) >= 9) {

	if (GRAPHICS_VER(dev_priv) >= 9) {

		plane->tiled = val & PLANE_CTL_TILED_MASK;

		fmt = skl_format_to_drm(

			val & PLANE_CTL_FORMAT_MASK,
@@ -256,7 +256,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 
	}



	plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,

		(INTEL_GEN(dev_priv) >= 9) ?

		(GRAPHICS_VER(dev_priv) >= 9) ?

		(_PRI_PLANE_STRIDE_MASK >> 6) :

		_PRI_PLANE_STRIDE_MASK, plane->bpp);

drivers/gpu/drm/i915/gvt/gtt.c

+2 −2
Original line number Diff line number Diff line
@@ -1055,12 +1055,12 @@ static bool vgpu_ips_enabled(struct intel_vgpu *vgpu) 
{

	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;



	if (INTEL_GEN(dev_priv) == 9 || INTEL_GEN(dev_priv) == 10) {

	if (GRAPHICS_VER(dev_priv) == 9 || GRAPHICS_VER(dev_priv) == 10) {

		u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &

			GAMW_ECO_ENABLE_64K_IPS_FIELD;



		return ips == GAMW_ECO_ENABLE_64K_IPS_FIELD;

	} else if (INTEL_GEN(dev_priv) >= 11) {

	} else if (GRAPHICS_VER(dev_priv) >= 11) {

		/* 64K paging only controlled by IPS bit in PTE now. */

		return true;

	} else

drivers/gpu/drm/i915/gvt/handlers.c

+3 −3
Original line number Diff line number Diff line
@@ -220,7 +220,7 @@ static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, 
{

	u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;



	if (INTEL_GEN(vgpu->gvt->gt->i915) <= 10) {

	if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) {

		if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)

			gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);

		else if (!ips)
@@ -286,7 +286,7 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu, 
	old = vgpu_vreg(vgpu, offset);

	new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);



	if (INTEL_GEN(vgpu->gvt->gt->i915)  >=  9) {

	if (GRAPHICS_VER(vgpu->gvt->gt->i915)  >=  9) {

		switch (offset) {

		case FORCEWAKE_RENDER_GEN9_REG:

			ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
@@ -1174,7 +1174,7 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 
	write_vreg(vgpu, offset, p_data, bytes);

	data = vgpu_vreg(vgpu, offset);



	if ((INTEL_GEN(vgpu->gvt->gt->i915) >= 9)

	if ((GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9)

		&& offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {

		/* SKL DPB/C/D aux ctl register changed */

		return 0;