Commit d8a3f65f authored by Radhey Shyam Pandey's avatar Radhey Shyam Pandey Committed by Vinod Koul
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dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client 



Read DT property to check if AXI DMA is connected to streaming IP
i.e axiethernet. If connected i.e xlnx,axistream-connected property
is present in the dma node then pass AXI4-Stream control words to dma
client using metadata_ops dmaengine API.

If not connected then driver won't support metadata_ops dmaengine API
and continue to support all legacy usecases.

Signed-off-by: default avatarRadhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Link: https://lore.kernel.org/r/1691387509-2113129-4-git-send-email-radhey.shyam.pandey@amd.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent e8cfa385

drivers/dma/xilinx/xilinx_dma.c

+37 −0
Original line number Diff line number Diff line
@@ -493,6 +493,7 @@ struct xilinx_dma_config { 
 * @s2mm_chan_id: DMA s2mm channel identifier

 * @mm2s_chan_id: DMA mm2s channel identifier

 * @max_buffer_len: Max buffer length

 * @has_axistream_connected: AXI DMA connected to AXI Stream IP

 */

struct xilinx_dma_device {

	void __iomem *regs;
@@ -511,6 +512,7 @@ struct xilinx_dma_device { 
	u32 s2mm_chan_id;

	u32 mm2s_chan_id;

	u32 max_buffer_len;

	bool has_axistream_connected;

};



/* Macros */
@@ -623,6 +625,29 @@ static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, 
	}

}



/**

 * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length

 * @tx: async transaction descriptor

 * @payload_len: metadata payload length

 * @max_len: metadata max length

 * Return: The app field pointer.

 */

static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx,

					 size_t *payload_len, size_t *max_len)

{

	struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);

	struct xilinx_axidma_tx_segment *seg;



	*max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS;

	seg = list_first_entry(&desc->segments,

			       struct xilinx_axidma_tx_segment, node);

	return seg->hw.app;

}



static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = {

	.get_ptr = xilinx_dma_get_metadata_ptr,

};



/* -----------------------------------------------------------------------------

 * Descriptors and segments alloc and free

 */
@@ -2221,6 +2246,9 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( 
		segment->hw.control |= XILINX_DMA_BD_EOP;

	}



	if (chan->xdev->has_axistream_connected)

		desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops;



	return &desc->async_tx;



error:
@@ -3067,6 +3095,11 @@ static int xilinx_dma_probe(struct platform_device *pdev) 
		}

	}



	if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {

		xdev->has_axistream_connected =

			of_property_read_bool(node, "xlnx,axistream-connected");

	}



	if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {

		err = of_property_read_u32(node, "xlnx,num-fstores",

					   &num_frames);
@@ -3092,6 +3125,10 @@ static int xilinx_dma_probe(struct platform_device *pdev) 
	else

		xdev->ext_addr = false;



	/* Set metadata mode */

	if (xdev->has_axistream_connected)

		xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE;



	/* Set the dma mask bits */

	err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width));

	if (err < 0) {