Unverified Commit d8a3d8a7 authored by Jisheng Zhang's avatar Jisheng Zhang Committed by Palmer Dabbelt
Browse files

riscv: hwcap: make ISA extension ids can be used in asm 



So that ISA extensions can be used in assembly files, convert the
multi-letter RISC-V ISA extension IDs enums to macros.
In order to make them visible, move the #ifndef __ASSEMBLY__ guard
to a later point in the header

Signed-off-by: default avatarJisheng Zhang <jszhang@kernel.org>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230128172856.3814-4-jszhang@kernel.org


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 191b27c7

arch/riscv/include/asm/hwcap.h

+21 −24
Original line number Diff line number Diff line
@@ -12,20 +12,6 @@ 
#include <linux/bits.h>

#include <uapi/asm/hwcap.h>



#ifndef __ASSEMBLY__

#include <linux/jump_label.h>

/*

 * This yields a mask that user programs can use to figure out what

 * instruction set this cpu supports.

 */

#define ELF_HWCAP		(elf_hwcap)



enum {

	CAP_HWCAP = 1,

};



extern unsigned long elf_hwcap;



#define RISCV_ISA_EXT_a		('a' - 'a')

#define RISCV_ISA_EXT_c		('c' - 'a')

#define RISCV_ISA_EXT_d		('d' - 'a')
@@ -46,23 +32,34 @@ extern unsigned long elf_hwcap; 
#define RISCV_ISA_EXT_BASE 26



/*

 * This enum represent the logical ID for each multi-letter RISC-V ISA extension.

 * These macros represent the logical ID for each multi-letter RISC-V ISA extension.

 * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed

 * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter

 * extensions while all the multi-letter extensions should define the next

 * available logical extension id.

 * Entries are sorted alphabetically.

 */

enum riscv_isa_ext_id {

	RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,

	RISCV_ISA_EXT_SSTC,

	RISCV_ISA_EXT_SVINVAL,

	RISCV_ISA_EXT_SVPBMT,

	RISCV_ISA_EXT_ZICBOM,

	RISCV_ISA_EXT_ZIHINTPAUSE,

	RISCV_ISA_EXT_ID_MAX

#define RISCV_ISA_EXT_SSCOFPMF		26

#define RISCV_ISA_EXT_SSTC		27

#define RISCV_ISA_EXT_SVINVAL		28

#define RISCV_ISA_EXT_SVPBMT		29

#define RISCV_ISA_EXT_ZICBOM		30

#define RISCV_ISA_EXT_ZIHINTPAUSE	31



#ifndef __ASSEMBLY__

#include <linux/jump_label.h>

/*

 * This yields a mask that user programs can use to figure out what

 * instruction set this cpu supports.

 */

#define ELF_HWCAP		(elf_hwcap)



enum {

	CAP_HWCAP = 1,

};

static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX);



extern unsigned long elf_hwcap;





/*

 * This enum represents the logical ID for each RISC-V ISA extension static