Commit d894892d authored by Shay Drory's avatar Shay Drory Committed by Saeed Mahameed
Browse files

net/mlx5: Arm only EQs with EQEs 



Currently, when more than one EQ is sharing an IRQ, and this IRQ is
being interrupted, all the EQs sharing the IRQ will be armed. This is
done regardless of whether an EQ has EQE.
When multiple EQs are sharing an IRQ, one or more EQs can have valid
EQEs.

Signed-off-by: default avatarShay Drory <shayd@nvidia.com>
Reviewed-by: default avatarParav Pandit <parav@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent fe839516

drivers/net/ethernet/mellanox/mlx5/core/eq.c

+2 −4
Original line number Diff line number Diff line
@@ -136,7 +136,7 @@ static int mlx5_eq_comp_int(struct notifier_block *nb, 


	eqe = next_eqe_sw(eq);

	if (!eqe)

		goto out;

		return 0;



	do {

		struct mlx5_core_cq *cq;
@@ -161,8 +161,6 @@ static int mlx5_eq_comp_int(struct notifier_block *nb, 
		++eq->cons_index;



	} while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq)));



out:

	eq_update_ci(eq, 1);



	if (cqn != -1)
@@ -250,9 +248,9 @@ static int mlx5_eq_async_int(struct notifier_block *nb, 
		++eq->cons_index;



	} while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq)));

	eq_update_ci(eq, 1);



out:

	eq_update_ci(eq, 1);

	mlx5_eq_async_int_unlock(eq_async, recovery, &flags);



	return unlikely(recovery) ? num_eqes : 0;