Commit d8634928 authored Aug 02, 2023 by Otto Pflüger Committed by Bjorn Andersson Aug 13, 2023

clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC

This is the parent clock of gpll0_early, so it needs to be enabled
for gpll0_early to return the correct rate. Enable GPLL0_SLEEP_CLK_SRC
by adding its existing definition to the clock list.

This clock also doesn't work with clk_alpha_pll_ops, use
clk_branch_simple_ops instead to make it enable and disable correctly.

Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
Link: https://lore.kernel.org/r/20230802170317.205112-3-otto.pflueger@abscue.de

Signed-off-by: Bjorn Andersson <andersson@kernel.org>

parent 593576a3

drivers/clk/qcom/gcc-msm8917.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -64,7 +64,7 @@ static struct clk_alpha_pll gpll0_sleep_clk_src = {
		.index = DT_XO,
		},
		.num_parents = 1,
		.ops = &clk_alpha_pll_ops,
		.ops = &clk_branch_simple_ops,
		},
		},
		};
		@@ -3042,6 +3042,7 @@ static struct gdsc cpp_gdsc = {
		static struct clk_regmap *gcc_msm8917_clocks[] = {
		[GPLL0] = &gpll0.clkr,
		[GPLL0_EARLY] = &gpll0_early.clkr,
		[GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
		[GPLL3] = &gpll3.clkr,
		[GPLL3_EARLY] = &gpll3_early.clkr,
		[GPLL4] = &gpll4.clkr,