Commit d8602f8b authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge remote-tracking branch 'arm64/for-next/perf' into for-next/core

* arm64/for-next/perf:
  perf/imx_ddr: Add system PMU identifier for userspace
  bindings: perf: imx-ddr: add compatible string
  arm64: Fix build failure when HARDLOCKUP_DETECTOR_PERF is enabled
  arm64: Enable perf events based hard lockup detector
  perf/imx_ddr: Add stop event counters support for i.MX8MP
  perf/smmuv3: Support sysfs identifier file
  drivers/perf: hisi: Add identifier sysfs file
  perf: remove duplicate check on fwnode
  driver/perf: Add PMU driver for the ARM DMC-620 memory controller
parents ba4259a6 881b0520
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+3 −0
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@@ -15,6 +15,9 @@ properties:
      - enum:
          - fsl,imx8-ddr-pmu
          - fsl,imx8m-ddr-pmu
          - fsl,imx8mq-ddr-pmu
          - fsl,imx8mm-ddr-pmu
          - fsl,imx8mn-ddr-pmu
          - fsl,imx8mp-ddr-pmu
      - items:
          - enum:
+2 −0
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@@ -170,6 +170,8 @@ config ARM64
	select HAVE_NMI
	select HAVE_PATA_PLATFORM
	select HAVE_PERF_EVENTS
	select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI && HW_PERF_EVENTS
	select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI
	select HAVE_PERF_REGS
	select HAVE_PERF_USER_STACK_DUMP
	select HAVE_REGS_AND_STACK_ACCESS_API
+39 −2
Original line number Diff line number Diff line
@@ -23,6 +23,8 @@
#include <linux/platform_device.h>
#include <linux/sched_clock.h>
#include <linux/smp.h>
#include <linux/nmi.h>
#include <linux/cpufreq.h>

/* ARMv8 Cortex-A53 specific event types. */
#define ARMV8_A53_PERFCTR_PREF_LINEFILL				0xC2
@@ -1248,10 +1250,21 @@ static struct platform_driver armv8_pmu_driver = {

static int __init armv8_pmu_driver_init(void)
{
	int ret;

	if (acpi_disabled)
		return platform_driver_register(&armv8_pmu_driver);
		ret = platform_driver_register(&armv8_pmu_driver);
	else
		return arm_pmu_acpi_probe(armv8_pmuv3_init);
		ret = arm_pmu_acpi_probe(armv8_pmuv3_init);

	/*
	 * Try to re-initialize lockup detector after PMU init in
	 * case PMU events are triggered via NMIs.
	 */
	if (ret == 0 && arm_pmu_irq_is_nmi())
		lockup_detector_init();

	return ret;
}
device_initcall(armv8_pmu_driver_init)

@@ -1309,3 +1322,27 @@ void arch_perf_update_userpage(struct perf_event *event,
	userpg->cap_user_time_zero = 1;
	userpg->cap_user_time_short = 1;
}

#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
/*
 * Safe maximum CPU frequency in case a particular platform doesn't implement
 * cpufreq driver. Although, architecture doesn't put any restrictions on
 * maximum frequency but 5 GHz seems to be safe maximum given the available
 * Arm CPUs in the market which are clocked much less than 5 GHz. On the other
 * hand, we can't make it much higher as it would lead to a large hard-lockup
 * detection timeout on parts which are running slower (eg. 1GHz on
 * Developerbox) and doesn't possess a cpufreq driver.
 */
#define SAFE_MAX_CPU_FREQ	5000000000UL // 5 GHz
u64 hw_nmi_get_sample_period(int watchdog_thresh)
{
	unsigned int cpu = smp_processor_id();
	unsigned long max_cpu_freq;

	max_cpu_freq = cpufreq_get_hw_max_freq(cpu) * 1000UL;
	if (!max_cpu_freq)
		max_cpu_freq = SAFE_MAX_CPU_FREQ;

	return (u64)max_cpu_freq * watchdog_thresh;
}
#endif
+7 −0
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@@ -130,6 +130,13 @@ config ARM_SPE_PMU
	  Extension, which provides periodic sampling of operations in
	  the CPU pipeline and reports this via the perf AUX interface.

config ARM_DMC620_PMU
	tristate "Enable PMU support for the ARM DMC-620 memory controller"
	depends on (ARM64 && ACPI) || COMPILE_TEST
	help
	  Support for PMU events monitoring on the ARM DMC-620 memory
	  controller.

source "drivers/perf/hisilicon/Kconfig"

endmenu
+1 −0
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@@ -13,3 +13,4 @@ obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o
obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o
obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o
obj-$(CONFIG_ARM_DMC620_PMU) += arm_dmc620_pmu.o
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