Commit d8405c63 authored Nov 28, 2023 by Mark Brown Committed by yanhaitao Nov 29, 2023

arm64/sve: Split _sve_flush macro into separate Z and predicate flushes

mainline inclusion
from mainline-v5.14-rc1
commit 483dbf6a
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8E73O
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=483dbf6a35907610597fdc304bd32ecba40cdff0



-------------------------------------------------

Trivial refactoring to support further work, no change to generated code.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210512151131.27877-2-broonie@kernel.org


Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Wang ShaoBo <bobo.shaobowang@huawei.com>

parent adacae35

arch/arm64/include/asm/fpsimdmacros.h

+3 −1

Original line number	Diff line number	Diff line
		@@ -211,8 +211,10 @@
		mov v\nz\().16b, v\nz\().16b
		.endm

		.macro sve_flush
		.macro sve_flush_z
		_for n, 0, 31, _sve_flush_z \n
		.endm
		.macro sve_flush_p_ffr
		_for n, 0, 15, _sve_pfalse \n
		_sve_wrffr 0
		.endm

arch/arm64/kernel/entry-fpsimd.S

+2 −1

Original line number	Diff line number	Diff line
		@@ -72,7 +72,8 @@ SYM_FUNC_END(sve_load_from_fpsimd_state)

		/* Zero all SVE registers but the first 128-bits of each vector */
		SYM_FUNC_START(sve_flush_live)
		sve_flush
		sve_flush_z
		sve_flush_p_ffr
		ret
		SYM_FUNC_END(sve_flush_live)