Commit d83b8aa5 authored by Colin Ian King's avatar Colin Ian King Committed by David S. Miller
Browse files

net: davinci_emac: Fix incorrect masking of tx and rx error channel 



The bit-masks used for the TXERRCH and RXERRCH (tx and rx error channels)
are incorrect and always lead to a zero result. The mask values are
currently the incorrect post-right shifted values, fix this by setting
them to the currect values.

(I double checked these against the TMS320TCI6482 data sheet, section
5.30, page 127 to ensure I had the correct mask values for the TXERRCH
and RXERRCH fields in the MACSTATUS register).

Addresses-Coverity: ("Operands don't affect result")
Fixes: a6286ee6 ("net: Add TI DaVinci EMAC driver")
Signed-off-by: default avatarColin Ian King <colin.king@canonical.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 33398048

drivers/net/ethernet/ti/davinci_emac.c

+2 −2
Original line number Diff line number Diff line
@@ -169,11 +169,11 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; 
/* EMAC mac_status register */

#define EMAC_MACSTATUS_TXERRCODE_MASK	(0xF00000)

#define EMAC_MACSTATUS_TXERRCODE_SHIFT	(20)

#define EMAC_MACSTATUS_TXERRCH_MASK	(0x7)

#define EMAC_MACSTATUS_TXERRCH_MASK	(0x70000)

#define EMAC_MACSTATUS_TXERRCH_SHIFT	(16)

#define EMAC_MACSTATUS_RXERRCODE_MASK	(0xF000)

#define EMAC_MACSTATUS_RXERRCODE_SHIFT	(12)

#define EMAC_MACSTATUS_RXERRCH_MASK	(0x7)

#define EMAC_MACSTATUS_RXERRCH_MASK	(0x700)

#define EMAC_MACSTATUS_RXERRCH_SHIFT	(8)



/* EMAC RX register masks */