Commit d81f78b4 authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: simplify IH programming 



Calculate all the addresses and pointers in amdgpu_ih.c

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8bb9eb48

drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c

+23 −11
Original line number Diff line number Diff line
@@ -52,6 +52,8 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 
	ih->use_bus_addr = use_bus_addr;



	if (use_bus_addr) {

		dma_addr_t dma_addr;



		if (ih->ring)

			return 0;
@@ -59,21 +61,26 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 
		 * add them to the end of the ring allocation.

		 */

		ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,

					      &ih->rb_dma_addr, GFP_KERNEL);

					      &dma_addr, GFP_KERNEL);

		if (ih->ring == NULL)

			return -ENOMEM;



		memset((void *)ih->ring, 0, ih->ring_size + 8);

		ih->wptr_offs = (ih->ring_size / 4) + 0;

		ih->rptr_offs = (ih->ring_size / 4) + 1;

		ih->gpu_addr = dma_addr;

		ih->wptr_addr = dma_addr + ih->ring_size;

		ih->wptr_cpu = &ih->ring[ih->ring_size / 4];

		ih->rptr_addr = dma_addr + ih->ring_size + 4;

		ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1];

	} else {

		r = amdgpu_device_wb_get(adev, &ih->wptr_offs);

		unsigned wptr_offs, rptr_offs;



		r = amdgpu_device_wb_get(adev, &wptr_offs);

		if (r)

			return r;



		r = amdgpu_device_wb_get(adev, &ih->rptr_offs);

		r = amdgpu_device_wb_get(adev, &rptr_offs);

		if (r) {

			amdgpu_device_wb_free(adev, ih->wptr_offs);

			amdgpu_device_wb_free(adev, wptr_offs);

			return r;

		}
@@ -82,10 +89,15 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 
					    &ih->ring_obj, &ih->gpu_addr,

					    (void **)&ih->ring);

		if (r) {

			amdgpu_device_wb_free(adev, ih->rptr_offs);

			amdgpu_device_wb_free(adev, ih->wptr_offs);

			amdgpu_device_wb_free(adev, rptr_offs);

			amdgpu_device_wb_free(adev, wptr_offs);

			return r;

		}



		ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;

		ih->wptr_cpu = &adev->wb.wb[wptr_offs];

		ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;

		ih->rptr_cpu = &adev->wb.wb[rptr_offs];

	}

	return 0;

}
@@ -109,13 +121,13 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) 
		 * add them to the end of the ring allocation.

		 */

		dma_free_coherent(adev->dev, ih->ring_size + 8,

				  (void *)ih->ring, ih->rb_dma_addr);

				  (void *)ih->ring, ih->gpu_addr);

		ih->ring = NULL;

	} else {

		amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,

				      (void **)&ih->ring);

		amdgpu_device_wb_free(adev, ih->wptr_offs);

		amdgpu_device_wb_free(adev, ih->rptr_offs);

		amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);

		amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);

	}

}

drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h

+14 −9
Original line number Diff line number Diff line
@@ -31,20 +31,25 @@ struct amdgpu_iv_entry; 
 * R6xx+ IH ring

 */

struct amdgpu_ih_ring {

	struct amdgpu_bo	*ring_obj;

	volatile uint32_t	*ring;

	unsigned		rptr;

	unsigned		ring_size;

	uint64_t		gpu_addr;

	uint32_t		ptr_mask;

	atomic_t		lock;

	bool                    enabled;

	unsigned		wptr_offs;

	unsigned		rptr_offs;

	u32			doorbell_index;

	bool			use_doorbell;

	bool			use_bus_addr;

	dma_addr_t		rb_dma_addr; /* only used when use_bus_addr = true */



	struct amdgpu_bo	*ring_obj;

	volatile uint32_t	*ring;

	uint64_t		gpu_addr;



	uint64_t		wptr_addr;

	volatile uint32_t	*wptr_cpu;



	uint64_t		rptr_addr;

	volatile uint32_t	*rptr_cpu;



	bool                    enabled;

	unsigned		rptr;

	atomic_t		lock;

};



/* provided by the ih block */

drivers/gpu/drm/amd/amdgpu/cik_ih.c

+4 −5
Original line number Diff line number Diff line
@@ -103,9 +103,9 @@ static void cik_ih_disable_interrupts(struct amdgpu_device *adev) 
 */

static int cik_ih_irq_init(struct amdgpu_device *adev)

{

	struct amdgpu_ih_ring *ih = &adev->irq.ih;

	int rb_bufsz;

	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

	u64 wptr_off;



	/* disable irqs */

	cik_ih_disable_interrupts(adev);
@@ -131,9 +131,8 @@ static int cik_ih_irq_init(struct amdgpu_device *adev) 
	ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK;



	/* set the writeback address whether it's enabled or not */

	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);

	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));

	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);



	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
@@ -188,7 +187,7 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev, 
{

	u32 wptr, tmp;



	wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);

	wptr = le32_to_cpu(*ih->wptr_cpu);



	if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {

		wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;

drivers/gpu/drm/amd/amdgpu/cz_ih.c

+5 −6
Original line number Diff line number Diff line
@@ -103,9 +103,9 @@ static void cz_ih_disable_interrupts(struct amdgpu_device *adev) 
 */

static int cz_ih_irq_init(struct amdgpu_device *adev)

{

	int rb_bufsz;

	struct amdgpu_ih_ring *ih = &adev->irq.ih;

	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

	u64 wptr_off;

	int rb_bufsz;



	/* disable irqs */

	cz_ih_disable_interrupts(adev);
@@ -133,9 +133,8 @@ static int cz_ih_irq_init(struct amdgpu_device *adev) 
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);



	/* set the writeback address whether it's enabled or not */

	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);

	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));

	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);



	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
@@ -190,7 +189,7 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev, 
{

	u32 wptr, tmp;



	wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);

	wptr = le32_to_cpu(*ih->wptr_cpu);



	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {

		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

+4 −5
Original line number Diff line number Diff line
@@ -103,9 +103,9 @@ static void iceland_ih_disable_interrupts(struct amdgpu_device *adev) 
 */

static int iceland_ih_irq_init(struct amdgpu_device *adev)

{

	struct amdgpu_ih_ring *ih = &adev->irq.ih;

	int rb_bufsz;

	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;

	u64 wptr_off;



	/* disable irqs */

	iceland_ih_disable_interrupts(adev);
@@ -133,9 +133,8 @@ static int iceland_ih_irq_init(struct amdgpu_device *adev) 
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);



	/* set the writeback address whether it's enabled or not */

	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);

	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));

	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);



	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
@@ -190,7 +189,7 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev, 
{

	u32 wptr, tmp;



	wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);

	wptr = le32_to_cpu(*ih->wptr_cpu);



	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {

		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);