Commit d81c203e authored by Takashi Iwai's avatar Takashi Iwai
Browse files

Merge tag 'asoc-fix-v6.5-merge-window' of... 

Merge tag 'asoc-fix-v6.5-merge-window' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus

ASoC: Fixes that got left after v6.4

These were some changes in my v6.4 branch that never got sent as fixes,
none of them super urgent thankfully.
parents 8d2a0cdf d900d9a4

sound/soc/codecs/cs43130.h

+69 −69
Original line number Diff line number Diff line
@@ -381,88 +381,88 @@ struct cs43130_clk_gen { 


/* frm_size = 16 */

static const struct cs43130_clk_gen cs43130_16_clk_gen[] = {

	{ 22579200,	32000,		.v = { 441,	10, }, },

	{ 22579200,	44100,		.v = { 32,	1, }, },

	{ 22579200,	48000,		.v = { 147,	5, }, },

	{ 22579200,	88200,		.v = { 16,	1, }, },

	{ 22579200,	96000,		.v = { 147,	10, }, },

	{ 22579200,	176400,		.v = { 8,	1, }, },

	{ 22579200,	192000,		.v = { 147,	20, }, },

	{ 22579200,	352800,		.v = { 4,	1, }, },

	{ 22579200,	384000,		.v = { 147,	40, }, },

	{ 24576000,	32000,		.v = { 48,	1, }, },

	{ 24576000,	44100,		.v = { 5120,	147, }, },

	{ 24576000,	48000,		.v = { 32,	1, }, },

	{ 24576000,	88200,		.v = { 2560,	147, }, },

	{ 24576000,	96000,		.v = { 16,	1, }, },

	{ 24576000,	176400,		.v = { 1280,	147, }, },

	{ 24576000,	192000,		.v = { 8,	1, }, },

	{ 24576000,	352800,		.v = { 640,	147, }, },

	{ 24576000,	384000,		.v = { 4,	1, }, },

	{ 22579200,	32000,		.v = { 10,	441, }, },

	{ 22579200,	44100,		.v = { 1,	32, }, },

	{ 22579200,	48000,		.v = { 5,	147, }, },

	{ 22579200,	88200,		.v = { 1,	16, }, },

	{ 22579200,	96000,		.v = { 10,	147, }, },

	{ 22579200,	176400,		.v = { 1,	8, }, },

	{ 22579200,	192000,		.v = { 20,	147, }, },

	{ 22579200,	352800,		.v = { 1,	4, }, },

	{ 22579200,	384000,		.v = { 40,	147, }, },

	{ 24576000,	32000,		.v = { 1,	48, }, },

	{ 24576000,	44100,		.v = { 147,	5120, }, },

	{ 24576000,	48000,		.v = { 1,	32, }, },

	{ 24576000,	88200,		.v = { 147,	2560, }, },

	{ 24576000,	96000,		.v = { 1,	16, }, },

	{ 24576000,	176400,		.v = { 147,	1280, }, },

	{ 24576000,	192000,		.v = { 1,	8, }, },

	{ 24576000,	352800,		.v = { 147,	640, }, },

	{ 24576000,	384000,		.v = { 1,	4, }, },

};



/* frm_size = 32 */

static const struct cs43130_clk_gen cs43130_32_clk_gen[] = {

	{ 22579200,	32000,		.v = { 441,	20, }, },

	{ 22579200,	44100,		.v = { 16,	1, }, },

	{ 22579200,	48000,		.v = { 147,	10, }, },

	{ 22579200,	88200,		.v = { 8,	1, }, },

	{ 22579200,	96000,		.v = { 147,	20, }, },

	{ 22579200,	176400,		.v = { 4,	1, }, },

	{ 22579200,	192000,		.v = { 147,	40, }, },

	{ 22579200,	352800,		.v = { 2,	1, }, },

	{ 22579200,	384000,		.v = { 147,	80, }, },

	{ 24576000,	32000,		.v = { 24,	1, }, },

	{ 24576000,	44100,		.v = { 2560,	147, }, },

	{ 24576000,	48000,		.v = { 16,	1, }, },

	{ 24576000,	88200,		.v = { 1280,	147, }, },

	{ 24576000,	96000,		.v = { 8,	1, }, },

	{ 24576000,	176400,		.v = { 640,	147, }, },

	{ 24576000,	192000,		.v = { 4,	1, }, },

	{ 24576000,	352800,		.v = { 320,	147, }, },

	{ 24576000,	384000,		.v = { 2,	1, }, },

	{ 22579200,	32000,		.v = { 20,	441, }, },

	{ 22579200,	44100,		.v = { 1,	16, }, },

	{ 22579200,	48000,		.v = { 10,	147, }, },

	{ 22579200,	88200,		.v = { 1,	8, }, },

	{ 22579200,	96000,		.v = { 20,	147, }, },

	{ 22579200,	176400,		.v = { 1,	4, }, },

	{ 22579200,	192000,		.v = { 40,	147, }, },

	{ 22579200,	352800,		.v = { 1,	2, }, },

	{ 22579200,	384000,		.v = { 80,	147, }, },

	{ 24576000,	32000,		.v = { 1,	24, }, },

	{ 24576000,	44100,		.v = { 147,	2560, }, },

	{ 24576000,	48000,		.v = { 1,	16, }, },

	{ 24576000,	88200,		.v = { 147,	1280, }, },

	{ 24576000,	96000,		.v = { 1,	8, }, },

	{ 24576000,	176400,		.v = { 147,	640, }, },

	{ 24576000,	192000,		.v = { 1,	4, }, },

	{ 24576000,	352800,		.v = { 147,	320, }, },

	{ 24576000,	384000,		.v = { 1,	2, }, },

};



/* frm_size = 48 */

static const struct cs43130_clk_gen cs43130_48_clk_gen[] = {

	{ 22579200,	32000,		.v = { 147,	100, }, },

	{ 22579200,	44100,		.v = { 32,	3, }, },

	{ 22579200,	48000,		.v = { 49,	5, }, },

	{ 22579200,	88200,		.v = { 16,	3, }, },

	{ 22579200,	96000,		.v = { 49,	10, }, },

	{ 22579200,	176400,		.v = { 8,	3, }, },

	{ 22579200,	192000,		.v = { 49,	20, }, },

	{ 22579200,	352800,		.v = { 4,	3, }, },

	{ 22579200,	384000,		.v = { 49,	40, }, },

	{ 24576000,	32000,		.v = { 16,	1, }, },

	{ 24576000,	44100,		.v = { 5120,	441, }, },

	{ 24576000,	48000,		.v = { 32,	3, }, },

	{ 24576000,	88200,		.v = { 2560,	441, }, },

	{ 24576000,	96000,		.v = { 16,	3, }, },

	{ 24576000,	176400,		.v = { 1280,	441, }, },

	{ 24576000,	192000,		.v = { 8,	3, }, },

	{ 24576000,	352800,		.v = { 640,	441, }, },

	{ 24576000,	384000,		.v = { 4,	3, }, },

	{ 22579200,	32000,		.v = { 100,	147, }, },

	{ 22579200,	44100,		.v = { 3,	32, }, },

	{ 22579200,	48000,		.v = { 5,	49, }, },

	{ 22579200,	88200,		.v = { 3,	16, }, },

	{ 22579200,	96000,		.v = { 10,	49, }, },

	{ 22579200,	176400,		.v = { 3,	8, }, },

	{ 22579200,	192000,		.v = { 20,	49, }, },

	{ 22579200,	352800,		.v = { 3,	4, }, },

	{ 22579200,	384000,		.v = { 40,	49, }, },

	{ 24576000,	32000,		.v = { 1,	16, }, },

	{ 24576000,	44100,		.v = { 441,	5120, }, },

	{ 24576000,	48000,		.v = { 3,	32, }, },

	{ 24576000,	88200,		.v = { 441,	2560, }, },

	{ 24576000,	96000,		.v = { 3,	16, }, },

	{ 24576000,	176400,		.v = { 441,	1280, }, },

	{ 24576000,	192000,		.v = { 3,	8, }, },

	{ 24576000,	352800,		.v = { 441,	640, }, },

	{ 24576000,	384000,		.v = { 3,	4, }, },

};



/* frm_size = 64 */

static const struct cs43130_clk_gen cs43130_64_clk_gen[] = {

	{ 22579200,	32000,		.v = { 441,	40, }, },

	{ 22579200,	44100,		.v = { 8,	1, }, },

	{ 22579200,	48000,		.v = { 147,	20, }, },

	{ 22579200,	88200,		.v = { 4,	1, }, },

	{ 22579200,	96000,		.v = { 147,	40, }, },

	{ 22579200,	176400,		.v = { 2,	1, }, },

	{ 22579200,	192000,		.v = { 147,	80, }, },

	{ 22579200,	32000,		.v = { 40,	441, }, },

	{ 22579200,	44100,		.v = { 1,	8, }, },

	{ 22579200,	48000,		.v = { 20,	147, }, },

	{ 22579200,	88200,		.v = { 1,	4, }, },

	{ 22579200,	96000,		.v = { 40,	147, }, },

	{ 22579200,	176400,		.v = { 1,	2, }, },

	{ 22579200,	192000,		.v = { 80,	147, }, },

	{ 22579200,	352800,		.v = { 1,	1, }, },

	{ 24576000,	32000,		.v = { 12,	1, }, },

	{ 24576000,	44100,		.v = { 1280,	147, }, },

	{ 24576000,	48000,		.v = { 8,	1, }, },

	{ 24576000,	88200,		.v = { 640,	147, }, },

	{ 24576000,	96000,		.v = { 4,	1, }, },

	{ 24576000,	176400,		.v = { 320,	147, }, },

	{ 24576000,	192000,		.v = { 2,	1, }, },

	{ 24576000,	352800,		.v = { 160,	147, }, },

	{ 24576000,	32000,		.v = { 1,	12, }, },

	{ 24576000,	44100,		.v = { 147,	1280, }, },

	{ 24576000,	48000,		.v = { 1,	8, }, },

	{ 24576000,	88200,		.v = { 147,	640, }, },

	{ 24576000,	96000,		.v = { 1,	4, }, },

	{ 24576000,	176400,		.v = { 147,	320, }, },

	{ 24576000,	192000,		.v = { 1,	2, }, },

	{ 24576000,	352800,		.v = { 147,	160, }, },

	{ 24576000,	384000,		.v = { 1,	1, }, },

};

sound/soc/soc-compress.c

+1 −0
Original line number Diff line number Diff line
@@ -193,6 +193,7 @@ static int soc_compr_open_fe(struct snd_compr_stream *cstream) 
	snd_soc_dai_compr_shutdown(cpu_dai, cstream, 1);

out:

	dpcm_path_put(&list);

	snd_soc_dpcm_mutex_unlock(fe);

be_err:

	fe->dpcm[stream].runtime_update = SND_SOC_DPCM_UPDATE_NO;

	snd_soc_card_mutex_unlock(fe->card);

sound/soc/tegra/tegra210_sfc.c

+30 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
//

// tegra210_sfc.c - Tegra210 SFC driver

//

// Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.

// Copyright (c) 2021-2023 NVIDIA CORPORATION.  All rights reserved.



#include <linux/clk.h>

#include <linux/device.h>
@@ -42,6 +42,7 @@ static const int tegra210_sfc_rates[TEGRA210_SFC_NUM_RATES] = { 
	32000,

	44100,

	48000,

	64000,

	88200,

	96000,

	176400,
@@ -2857,6 +2858,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = { 
		coef_8to32,

		coef_8to44,

		coef_8to48,

		UNSUPP_CONV,

		coef_8to88,

		coef_8to96,

		UNSUPP_CONV,
@@ -2872,6 +2874,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = { 
		coef_11to32,

		coef_11to44,

		coef_11to48,

		UNSUPP_CONV,

		coef_11to88,

		coef_11to96,

		UNSUPP_CONV,
@@ -2887,6 +2890,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = { 
		coef_16to32,

		coef_16to44,

		coef_16to48,

		UNSUPP_CONV,

		coef_16to88,

		coef_16to96,

		coef_16to176,
@@ -2902,6 +2906,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = { 
		coef_22to32,

		coef_22to44,

		coef_22to48,

		UNSUPP_CONV,

		coef_22to88,

		coef_22to96,

		coef_22to176,
@@ -2917,6 +2922,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = { 
		coef_24to32,

		coef_24to44,

		coef_24to48,

		UNSUPP_CONV,

		coef_24to88,

		coef_24to96,

		coef_24to176,
@@ -2932,6 +2938,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = { 
		BYPASS_CONV,

		coef_32to44,

		coef_32to48,

		UNSUPP_CONV,

		coef_32to88,

		coef_32to96,

		coef_32to176,
@@ -2947,6 +2954,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = { 
		coef_44to32,

		BYPASS_CONV,

		coef_44to48,

		UNSUPP_CONV,

		coef_44to88,

		coef_44to96,

		coef_44to176,
@@ -2962,11 +2970,28 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = { 
		coef_48to32,

		coef_48to44,

		BYPASS_CONV,

		UNSUPP_CONV,

		coef_48to88,

		coef_48to96,

		coef_48to176,

		coef_48to192,

	},

	/* Convertions from 64 kHz */

	{

		UNSUPP_CONV,

		UNSUPP_CONV,

		UNSUPP_CONV,

		UNSUPP_CONV,

		UNSUPP_CONV,

		UNSUPP_CONV,

		UNSUPP_CONV,

		UNSUPP_CONV,

		UNSUPP_CONV,

		UNSUPP_CONV,

		UNSUPP_CONV,

		UNSUPP_CONV,

		UNSUPP_CONV,

	},

	/* Convertions from 88.2 kHz */

	{

		coef_88to8,
@@ -2977,6 +3002,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = { 
		coef_88to32,

		coef_88to44,

		coef_88to48,

		UNSUPP_CONV,

		BYPASS_CONV,

		coef_88to96,

		coef_88to176,
@@ -2991,6 +3017,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = { 
		coef_96to32,

		coef_96to44,

		coef_96to48,

		UNSUPP_CONV,

		coef_96to88,

		BYPASS_CONV,

		coef_96to176,
@@ -3006,6 +3033,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = { 
		coef_176to32,

		coef_176to44,

		coef_176to48,

		UNSUPP_CONV,

		coef_176to88,

		coef_176to96,

		BYPASS_CONV,
@@ -3021,6 +3049,7 @@ static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = { 
		coef_192to32,

		coef_192to44,

		coef_192to48,

		UNSUPP_CONV,

		coef_192to88,

		coef_192to96,

		coef_192to176,

sound/soc/tegra/tegra210_sfc.h

+2 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * tegra210_sfc.h - Definitions for Tegra210 SFC driver

 *

 * Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.

 * Copyright (c) 2021-2023 NVIDIA CORPORATION.  All rights reserved.

 *

 */
@@ -47,7 +47,7 @@ 
#define TEGRA210_SFC_EN_SHIFT			0

#define TEGRA210_SFC_EN				(1 << TEGRA210_SFC_EN_SHIFT)



#define TEGRA210_SFC_NUM_RATES 12

#define TEGRA210_SFC_NUM_RATES 13



/* Fields in TEGRA210_SFC_COEF_RAM */

#define TEGRA210_SFC_COEF_RAM_EN		BIT(0)