Commit d7ea31ca authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'fpga-late-for-5.13' of... 

Merge tag 'fpga-late-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga

 into char-misc-next

Moritz writes:

Second set of FPGA Manager changes for 5.13-rc1

FPGA Manager:
- Russ' first change improves port_enable reliability
- Russ' second change adds a new device ID for a DFL device
- Geert's change updates the examples in binding with dt overlay sugar
  syntax

All patches have been reviewed on the mailing list, and have been in the
last linux-next releases (as part of my for-next branch) without issues.

Signed-off-by: default avatarMoritz Fischer <mdf@kernel.org>

* tag 'fpga-late-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga:
  fpga: dfl: pci: add DID for D5005 PAC cards
  dt-bindings: fpga: fpga-region: Convert to sugar syntax
  fpga: dfl: afu: harden port enable logic
  fpga: Add support for Xilinx DFX AXI Shutdown manager
  dt-bindings: fpga: Add compatible value for Xilinx DFX AXI shutdown manager
  fpga: xilinx-pr-decoupler: Simplify code by using dev_err_probe()
  fpga: fpga-mgr: xilinx-spi: fix error messages on -EPROBE_DEFER
parents e76e8b56 a78a51a8

Documentation/devicetree/bindings/fpga/fpga-region.txt

+85 −102
Original line number Diff line number Diff line
@@ -245,13 +245,10 @@ Base tree contains: 


Overlay contains:



/dts-v1/ /plugin/;

/ {

	fragment@0 {

		target = <&fpga_region0>;

		#address-cells = <1>;

		#size-cells = <1>;

		__overlay__ {

/dts-v1/;

/plugin/;



&fpga_region0 {

	#address-cells = <1>;

	#size-cells = <1>;
@@ -275,8 +272,6 @@ Overlay contains: 
		reg = <0x0 0x10000>;

	};

};

	};

};





Supported Use Models
@@ -371,13 +366,11 @@ Live Device Tree contains: 
	};



DT Overlay contains:

/dts-v1/ /plugin/;

/ {

fragment@0 {

	target = <&fpga_region0>;

	#address-cells = <1>;

	#size-cells = <1>;

	__overlay__ {



/dts-v1/;

/plugin/;



&fpga_region0 {

	#address-cells = <1>;

	#size-cells = <1>;
@@ -391,7 +384,6 @@ fragment@0 { 
		xlnx,gpio-width= <0x6>;

	};

};

};



Device Tree Example: Full Reconfiguration to add PRR's

======================================================
@@ -402,13 +394,11 @@ This example programs the FPGA to have two regions that can later be partially 
configured.  Each region has its own bridge in the FPGA fabric.



DT Overlay contains:

/dts-v1/ /plugin/;

/ {

	fragment@0 {

		target = <&fpga_region0>;

		#address-cells = <1>;

		#size-cells = <1>;

		__overlay__ {



/dts-v1/;

/plugin/;



&fpga_region0 {

	#address-cells = <1>;

	#size-cells = <1>;
@@ -438,8 +428,6 @@ DT Overlay contains: 
		};

	};

};

	};

};



Device Tree Example: Partial Reconfiguration

============================================
@@ -451,13 +439,10 @@ differences are that the FPGA is partially reconfigured due to the 
"partial-fpga-config" boolean and the only bridge that is controlled during

programming is the FPGA based bridge of fpga_region1.



/dts-v1/ /plugin/;

/ {

	fragment@0 {

		target = <&fpga_region1>;

		#address-cells = <1>;

		#size-cells = <1>;

		__overlay__ {

/dts-v1/;

/plugin/;



&fpga_region1 {

	#address-cells = <1>;

	#size-cells = <1>;
@@ -473,8 +458,6 @@ programming is the FPGA based bridge of fpga_region1. 
		gpio-controller;

	};

};

	};

};



Constraints

===========

drivers/fpga/dfl-afu-error.c

+6 −4
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ static int afu_port_err_clear(struct device *dev, u64 err) 
	struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);

	struct platform_device *pdev = to_platform_device(dev);

	void __iomem *base_err, *base_hdr;

	int ret = -EBUSY;

	int enable_ret = 0, ret = -EBUSY;

	u64 v;



	base_err = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
@@ -96,18 +96,20 @@ static int afu_port_err_clear(struct device *dev, u64 err) 
		v = readq(base_err + PORT_FIRST_ERROR);

		writeq(v, base_err + PORT_FIRST_ERROR);

	} else {

		dev_warn(dev, "%s: received 0x%llx, expected 0x%llx\n",

			 __func__, v, err);

		ret = -EINVAL;

	}



	/* Clear mask */

	__afu_port_err_mask(dev, false);



	/* Enable the Port by clear the reset */

	__afu_port_enable(pdev);

	/* Enable the Port by clearing the reset */

	enable_ret = __afu_port_enable(pdev);



done:

	mutex_unlock(&pdata->lock);

	return ret;

	return enable_ret ? enable_ret : ret;

}



static ssize_t errors_show(struct device *dev, struct device_attribute *attr,

drivers/fpga/dfl-afu-main.c

+24 −11
Original line number Diff line number Diff line
@@ -21,6 +21,9 @@ 


#include "dfl-afu.h"



#define RST_POLL_INVL 10 /* us */

#define RST_POLL_TIMEOUT 1000 /* us */



/**

 * __afu_port_enable - enable a port by clear reset

 * @pdev: port platform device.
@@ -32,7 +35,7 @@ 
 *

 * The caller needs to hold lock for protection.

 */

void __afu_port_enable(struct platform_device *pdev)

int __afu_port_enable(struct platform_device *pdev)

{

	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);

	void __iomem *base;
@@ -41,7 +44,7 @@ void __afu_port_enable(struct platform_device *pdev) 
	WARN_ON(!pdata->disable_count);



	if (--pdata->disable_count != 0)

		return;

		return 0;



	base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER);
@@ -49,10 +52,20 @@ void __afu_port_enable(struct platform_device *pdev) 
	v = readq(base + PORT_HDR_CTRL);

	v &= ~PORT_CTRL_SFTRST;

	writeq(v, base + PORT_HDR_CTRL);



	/*

	 * HW clears the ack bit to indicate that the port is fully out

	 * of reset.

	 */

	if (readq_poll_timeout(base + PORT_HDR_CTRL, v,

			       !(v & PORT_CTRL_SFTRST_ACK),

			       RST_POLL_INVL, RST_POLL_TIMEOUT)) {

		dev_err(&pdev->dev, "timeout, failure to enable device\n");

		return -ETIMEDOUT;

	}



#define RST_POLL_INVL 10 /* us */

#define RST_POLL_TIMEOUT 1000 /* us */

	return 0;

}



/**

 * __afu_port_disable - disable a port by hold reset
@@ -86,7 +99,7 @@ int __afu_port_disable(struct platform_device *pdev) 
	if (readq_poll_timeout(base + PORT_HDR_CTRL, v,

			       v & PORT_CTRL_SFTRST_ACK,

			       RST_POLL_INVL, RST_POLL_TIMEOUT)) {

		dev_err(&pdev->dev, "timeout, fail to reset device\n");

		dev_err(&pdev->dev, "timeout, failure to disable device\n");

		return -ETIMEDOUT;

	}
@@ -110,10 +123,10 @@ static int __port_reset(struct platform_device *pdev) 
	int ret;



	ret = __afu_port_disable(pdev);

	if (!ret)

		__afu_port_enable(pdev);



	if (ret)

		return ret;



	return __afu_port_enable(pdev);

}



static int port_reset(struct platform_device *pdev)
@@ -872,11 +885,11 @@ static int afu_dev_destroy(struct platform_device *pdev) 
static int port_enable_set(struct platform_device *pdev, bool enable)

{

	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);

	int ret = 0;

	int ret;



	mutex_lock(&pdata->lock);

	if (enable)

		__afu_port_enable(pdev);

		ret = __afu_port_enable(pdev);

	else

		ret = __afu_port_disable(pdev);

	mutex_unlock(&pdata->lock);

drivers/fpga/dfl-afu.h

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ struct dfl_afu { 
};



/* hold pdata->lock when call __afu_port_enable/disable */

void __afu_port_enable(struct platform_device *pdev);

int __afu_port_enable(struct platform_device *pdev);

int __afu_port_disable(struct platform_device *pdev);



void afu_mmio_region_init(struct dfl_feature_platform_data *pdata);

drivers/fpga/dfl-pci.c

+11 −7
Original line number Diff line number Diff line
@@ -73,10 +73,12 @@ static void cci_pci_free_irq(struct pci_dev *pcidev) 
#define PCIE_DEVICE_ID_PF_INT_6_X		0xBCC0

#define PCIE_DEVICE_ID_PF_DSC_1_X		0x09C4

#define PCIE_DEVICE_ID_INTEL_PAC_N3000		0x0B30

#define PCIE_DEVICE_ID_INTEL_PAC_D5005		0x0B2B

/* VF Device */

#define PCIE_DEVICE_ID_VF_INT_5_X		0xBCBF

#define PCIE_DEVICE_ID_VF_INT_6_X		0xBCC1

#define PCIE_DEVICE_ID_VF_DSC_1_X		0x09C5

#define PCIE_DEVICE_ID_INTEL_PAC_D5005_VF	0x0B2C



static struct pci_device_id cci_pcie_id_tbl[] = {

	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
@@ -86,6 +88,8 @@ static struct pci_device_id cci_pcie_id_tbl[] = { 
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},

	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},

	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),},

	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),},

	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),},

	{0,}

};

MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);