Loading Documentation/devicetree/bindings/clock/ti-clkctrl.txt +8 −3 Original line number Diff line number Diff line Loading @@ -16,18 +16,23 @@ For more information, please see the Linux clock framework binding at Documentation/devicetree/bindings/clock/clock-bindings.txt. Required properties : - compatible : shall be "ti,clkctrl" - compatible : shall be "ti,clkctrl" or a clock domain specific name: "ti,clkctrl-l4-cfg" "ti,clkctrl-l4-per" "ti,clkctrl-l4-secure" "ti,clkctrl-l4-wkup" - #clock-cells : shall contain 2 with the first entry being the instance offset from the clock domain base and the second being the clock index - reg : clock registers Example: Clock controller node on omap 4430: &cm2 { l4per: cm@1400 { cm_l4per@0 { cm_l4per_clkctrl: clk@20 { compatible = "ti,clkctrl"; cm_l4per_clkctrl: clock@20 { compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; reg = <0x20 0x1b0>; #clock-cells = <2>; }; Loading Documentation/devicetree/bindings/clock/ti/dra7-atl.txt +2 −2 Original line number Diff line number Diff line Loading @@ -43,7 +43,7 @@ Configuration of ATL instances: - aws : Audio word select signal selection }; For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include For valid word select signals, see the dt-bindings/clock/ti-dra7-atl.h include file. Examples: Loading Loading @@ -83,7 +83,7 @@ atl: atl@4843c000 { clock-names = "fck"; }; #include <dt-bindings/clk/ti-dra7-atl.h> #include <dt-bindings/clock/ti-dra7-atl.h> &atl { Loading arch/arm/boot/dts/am437x-sk-evm.dts +26 −1 Original line number Diff line number Diff line Loading @@ -272,6 +272,12 @@ >; }; clkout1_pin: pinmux_clkout1_pin { pinctrl-single,pins = < 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ Loading Loading @@ -593,6 +599,25 @@ pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; ov2659@30 { compatible = "ovti,ov2659"; reg = <0x30>; pinctrl-names = "default"; pinctrl-0 = <&clkout1_pin>; clocks = <&clkout1_mux_ck>; clock-names = "xvclk"; assigned-clocks = <&clkout1_mux_ck>; assigned-clock-parents = <&clkout1_osc_div_ck>; port { ov2659_1: endpoint { remote-endpoint = <&vpfe0_ep>; link-frequencies = /bits/ 64 <70000000>; }; }; }; edt-ft5306@38 { status = "okay"; compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; Loading Loading @@ -877,7 +902,7 @@ /* Camera port */ port { vpfe0_ep: endpoint { /* remote-endpoint = <&sensor>; add once we have it */ remote-endpoint = <&ov2659_1>; ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; Loading arch/arm/boot/dts/am43x-epos-evm.dts +22 −1 Original line number Diff line number Diff line Loading @@ -145,6 +145,12 @@ system-clock-frequency = <12000000>; }; }; audio_mstrclk: clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <12000000>; }; }; &am43xx_pinmux { Loading Loading @@ -696,6 +702,21 @@ IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ }; ov2659@30 { compatible = "ovti,ov2659"; reg = <0x30>; clocks = <&audio_mstrclk>; clock-names = "xvclk"; port { ov2659_1: endpoint { remote-endpoint = <&vpfe1_ep>; link-frequencies = /bits/ 64 <70000000>; }; }; }; }; &i2c2 { Loading Loading @@ -962,7 +983,7 @@ port { vpfe1_ep: endpoint { /* remote-endpoint = <&sensor>; add once we have it */ remote-endpoint = <&ov2659_1>; ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; Loading arch/arm/boot/dts/am43xx-clocks.dtsi +54 −0 Original line number Diff line number Diff line Loading @@ -704,6 +704,60 @@ ti,bit-shift = <8>; reg = <0x2a48>; }; clkout1_osc_div_ck: clkout1-osc-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin_ck>; ti,bit-shift = <20>; ti,max-div = <4>; reg = <0x4100>; }; clkout1_src2_mux_ck: clkout1-src2-mux-ck { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, <&dpll_mpu_m2_ck>; reg = <0x4100>; }; clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&clkout1_src2_mux_ck>; ti,bit-shift = <4>; ti,max-div = <8>; reg = <0x4100>; }; clkout1_src2_post_div_ck: clkout1-src2-post-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&clkout1_src2_pre_div_ck>; ti,bit-shift = <8>; ti,max-div = <32>; ti,index-power-of-two; reg = <0x4100>; }; clkout1_mux_ck: clkout1-mux-ck { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; ti,bit-shift = <16>; reg = <0x4100>; }; clkout1_ck: clkout1-ck { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkout1_mux_ck>; ti,bit-shift = <23>; reg = <0x4100>; }; }; &prcm { Loading Loading
Documentation/devicetree/bindings/clock/ti-clkctrl.txt +8 −3 Original line number Diff line number Diff line Loading @@ -16,18 +16,23 @@ For more information, please see the Linux clock framework binding at Documentation/devicetree/bindings/clock/clock-bindings.txt. Required properties : - compatible : shall be "ti,clkctrl" - compatible : shall be "ti,clkctrl" or a clock domain specific name: "ti,clkctrl-l4-cfg" "ti,clkctrl-l4-per" "ti,clkctrl-l4-secure" "ti,clkctrl-l4-wkup" - #clock-cells : shall contain 2 with the first entry being the instance offset from the clock domain base and the second being the clock index - reg : clock registers Example: Clock controller node on omap 4430: &cm2 { l4per: cm@1400 { cm_l4per@0 { cm_l4per_clkctrl: clk@20 { compatible = "ti,clkctrl"; cm_l4per_clkctrl: clock@20 { compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; reg = <0x20 0x1b0>; #clock-cells = <2>; }; Loading
Documentation/devicetree/bindings/clock/ti/dra7-atl.txt +2 −2 Original line number Diff line number Diff line Loading @@ -43,7 +43,7 @@ Configuration of ATL instances: - aws : Audio word select signal selection }; For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include For valid word select signals, see the dt-bindings/clock/ti-dra7-atl.h include file. Examples: Loading Loading @@ -83,7 +83,7 @@ atl: atl@4843c000 { clock-names = "fck"; }; #include <dt-bindings/clk/ti-dra7-atl.h> #include <dt-bindings/clock/ti-dra7-atl.h> &atl { Loading
arch/arm/boot/dts/am437x-sk-evm.dts +26 −1 Original line number Diff line number Diff line Loading @@ -272,6 +272,12 @@ >; }; clkout1_pin: pinmux_clkout1_pin { pinctrl-single,pins = < 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ Loading Loading @@ -593,6 +599,25 @@ pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; ov2659@30 { compatible = "ovti,ov2659"; reg = <0x30>; pinctrl-names = "default"; pinctrl-0 = <&clkout1_pin>; clocks = <&clkout1_mux_ck>; clock-names = "xvclk"; assigned-clocks = <&clkout1_mux_ck>; assigned-clock-parents = <&clkout1_osc_div_ck>; port { ov2659_1: endpoint { remote-endpoint = <&vpfe0_ep>; link-frequencies = /bits/ 64 <70000000>; }; }; }; edt-ft5306@38 { status = "okay"; compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; Loading Loading @@ -877,7 +902,7 @@ /* Camera port */ port { vpfe0_ep: endpoint { /* remote-endpoint = <&sensor>; add once we have it */ remote-endpoint = <&ov2659_1>; ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; Loading
arch/arm/boot/dts/am43x-epos-evm.dts +22 −1 Original line number Diff line number Diff line Loading @@ -145,6 +145,12 @@ system-clock-frequency = <12000000>; }; }; audio_mstrclk: clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <12000000>; }; }; &am43xx_pinmux { Loading Loading @@ -696,6 +702,21 @@ IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ }; ov2659@30 { compatible = "ovti,ov2659"; reg = <0x30>; clocks = <&audio_mstrclk>; clock-names = "xvclk"; port { ov2659_1: endpoint { remote-endpoint = <&vpfe1_ep>; link-frequencies = /bits/ 64 <70000000>; }; }; }; }; &i2c2 { Loading Loading @@ -962,7 +983,7 @@ port { vpfe1_ep: endpoint { /* remote-endpoint = <&sensor>; add once we have it */ remote-endpoint = <&ov2659_1>; ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; Loading
arch/arm/boot/dts/am43xx-clocks.dtsi +54 −0 Original line number Diff line number Diff line Loading @@ -704,6 +704,60 @@ ti,bit-shift = <8>; reg = <0x2a48>; }; clkout1_osc_div_ck: clkout1-osc-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin_ck>; ti,bit-shift = <20>; ti,max-div = <4>; reg = <0x4100>; }; clkout1_src2_mux_ck: clkout1-src2-mux-ck { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, <&dpll_mpu_m2_ck>; reg = <0x4100>; }; clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&clkout1_src2_mux_ck>; ti,bit-shift = <4>; ti,max-div = <8>; reg = <0x4100>; }; clkout1_src2_post_div_ck: clkout1-src2-post-div-ck { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&clkout1_src2_pre_div_ck>; ti,bit-shift = <8>; ti,max-div = <32>; ti,index-power-of-two; reg = <0x4100>; }; clkout1_mux_ck: clkout1-mux-ck { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; ti,bit-shift = <16>; reg = <0x4100>; }; clkout1_ck: clkout1-ck { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkout1_mux_ck>; ti,bit-shift = <23>; reg = <0x4100>; }; }; &prcm { Loading