Commit d735599a authored by Athira Rajeev's avatar Athira Rajeev Committed by Michael Ellerman
Browse files

powerpc/perf: Add extended regs support for power10 platform 



Include capability flag PERF_PMU_CAP_EXTENDED_REGS for power10 and
expose MMCR3, SIER2, SIER3 registers as part of extended regs. Also
introduce PERF_REG_PMU_MASK_31 to define extended mask value at
runtime for power10.

Suggested-by: default avatarRyan Grimm <grimm@linux.ibm.com>
Signed-off-by: default avatarAthira Rajeev <atrajeev@linux.vnet.ibm.com>
Tested-by: default avatarNageswara R Sastry <nasastry@in.ibm.com>
Reviewed-by: default avatarKajol Jain <kjain@linux.ibm.com>
Reviewed-and-tested-by: default avatarRavi Bangoria <ravi.bangoria@linux.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1596794701-23530-3-git-send-email-atrajeev@linux.vnet.ibm.com
parent 781fa481

arch/powerpc/include/uapi/asm/perf_regs.h

+6 −0
Original line number Diff line number Diff line
@@ -52,6 +52,9 @@ enum perf_event_powerpc_regs { 
	PERF_REG_POWERPC_MMCR0,

	PERF_REG_POWERPC_MMCR1,

	PERF_REG_POWERPC_MMCR2,

	PERF_REG_POWERPC_MMCR3,

	PERF_REG_POWERPC_SIER2,

	PERF_REG_POWERPC_SIER3,

	/* Max regs without the extended regs */

	PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,

};
@@ -60,6 +63,9 @@ enum perf_event_powerpc_regs { 


/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */

#define PERF_REG_PMU_MASK_300   (((1ULL << (PERF_REG_POWERPC_MMCR2 + 1)) - 1) - PERF_REG_PMU_MASK)

/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 */

#define PERF_REG_PMU_MASK_31   (((1ULL << (PERF_REG_POWERPC_SIER3 + 1)) - 1) - PERF_REG_PMU_MASK)



#define PERF_REG_MAX_ISA_300   (PERF_REG_POWERPC_MMCR2 + 1)

#define PERF_REG_MAX_ISA_31    (PERF_REG_POWERPC_SIER3 + 1)

#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */

arch/powerpc/perf/perf_regs.c

+11 −1
Original line number Diff line number Diff line
@@ -81,6 +81,14 @@ static u64 get_ext_regs_value(int idx) 
		return mfspr(SPRN_MMCR1);

	case PERF_REG_POWERPC_MMCR2:

		return mfspr(SPRN_MMCR2);

#ifdef CONFIG_PPC64

	case PERF_REG_POWERPC_MMCR3:

		return mfspr(SPRN_MMCR3);

	case PERF_REG_POWERPC_SIER2:

		return mfspr(SPRN_SIER2);

	case PERF_REG_POWERPC_SIER3:

		return mfspr(SPRN_SIER3);

#endif

	default: return 0;

	}

}
@@ -89,7 +97,9 @@ u64 perf_reg_value(struct pt_regs *regs, int idx) 
{

	u64 perf_reg_extended_max = PERF_REG_POWERPC_MAX;



	if (cpu_has_feature(CPU_FTR_ARCH_300))

	if (cpu_has_feature(CPU_FTR_ARCH_31))

		perf_reg_extended_max = PERF_REG_MAX_ISA_31;

	else if (cpu_has_feature(CPU_FTR_ARCH_300))

		perf_reg_extended_max = PERF_REG_MAX_ISA_300;



	if (idx == PERF_REG_POWERPC_SIER &&

arch/powerpc/perf/power10-pmu.c

+6 −0
Original line number Diff line number Diff line
@@ -87,6 +87,8 @@ 
#define POWER10_MMCRA_IFM3		0x00000000C0000000UL

#define POWER10_MMCRA_BHRB_MASK		0x00000000C0000000UL



extern u64 PERF_REG_EXTENDED_MASK;



/* Table of alternatives, sorted by column 0 */

static const unsigned int power10_event_alternatives[][MAX_ALT] = {

	{ PM_RUN_CYC_ALT,		PM_RUN_CYC },
@@ -397,6 +399,7 @@ static struct power_pmu power10_pmu = { 
	.cache_events		= &power10_cache_events,

	.attr_groups		= power10_pmu_attr_groups,

	.bhrb_nr		= 32,

	.capabilities           = PERF_PMU_CAP_EXTENDED_REGS,

};



int init_power10_pmu(void)
@@ -408,6 +411,9 @@ int init_power10_pmu(void) 
	    strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power10"))

		return -ENODEV;



	/* Set the PERF_REG_EXTENDED_MASK here */

	PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_31;



	rc = register_power_pmu(&power10_pmu);

	if (rc)

		return rc;