Unverified Commit d72f365e authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!8819 Add support for Hygon model 7h processors 

Merge Pull Request from: @liao-xuan1 
 
Update L3 PMU and NB, EDAC drivers for Hygon family 18h model 7h processors.

Reference:
https://gitee.com/deepin-kernelsig/kernel/pulls/1
https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel/pulls/54 
 
Link:https://gitee.com/openeuler/kernel/pulls/8819

 

Reviewed-by: default avatarZhang Peng <zhangpeng362@huawei.com>
Reviewed-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents 5aea5388 74a5843c

arch/x86/events/amd/uncore.c

+4 −3
Original line number Diff line number Diff line
@@ -250,7 +250,8 @@ amd_f17h_uncore_is_visible(struct kobject *kobj, struct attribute *attr, int i) 
static umode_t

hygon_f18h_m6h_uncore_is_visible(struct kobject *kobj, struct attribute *attr, int i)

{

	return boot_cpu_data.x86 == 0x18 && boot_cpu_data.x86_model == 0x6 ?

	return boot_cpu_data.x86 == 0x18 &&

	       boot_cpu_data.x86_model >= 0x6 && boot_cpu_data.x86_model <= 0xf	?

	       attr->mode : 0;

}
@@ -774,7 +775,7 @@ static int amd_uncore_l3_event_init(struct perf_event *event) 
		       ((config & AMD64_L3_THREAD_MASK) ? : AMD64_L3_THREAD_MASK);

	else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&

		 boot_cpu_data.x86 == 0x18) {

		if (boot_cpu_data.x86_model == 0x6)

		if (boot_cpu_data.x86_model >= 0x6 && boot_cpu_data.x86_model <= 0xf)

			return ((config & HYGON_L3_SLICE_MASK) ? : HYGON_L3_SLICE_MASK) |

			       ((config & HYGON_L3_THREAD_MASK) ? : HYGON_L3_THREAD_MASK);

		else
@@ -878,7 +879,7 @@ int amd_uncore_l3_ctx_init(struct amd_uncore *uncore, unsigned int cpu) 
	    boot_cpu_data.x86 == 0x18) {

		*l3_attr++ = &format_attr_event8.attr;

		*l3_attr++ = &format_attr_umask8.attr;

		if (boot_cpu_data.x86_model == 0x6) {

		if (boot_cpu_data.x86_model >= 0x6 && boot_cpu_data.x86_model <= 0xf) {

			*l3_attr++ = &format_attr_threadmask32.attr;

			pmu->pmu.attr_update = hygon_uncore_l3_attr_update;

		} else {

arch/x86/kernel/amd_nb.c

+4 −1
Original line number Diff line number Diff line
@@ -282,6 +282,7 @@ static int get_df_register(struct pci_dev *misc, u8 func, int offset, u32 *value 
				device = PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1;

			break;

		case 0x6:

		case 0x7:

			device = PCI_DEVICE_ID_HYGON_18H_M05H_DF_F1;

			break;

		default:
@@ -290,6 +291,7 @@ static int get_df_register(struct pci_dev *misc, u8 func, int offset, u32 *value 
	} else if (func == 5) {

		switch (boot_cpu_data.x86_model) {

		case 0x6:

		case 0x7:

			device = PCI_DEVICE_ID_HYGON_18H_M06H_DF_F5;

			break;

		default:
@@ -322,7 +324,8 @@ int get_df_id(struct pci_dev *misc, u8 *id) 
	u32 value;

	int ret;



	if (boot_cpu_data.x86_model == 0x6) {

	if (boot_cpu_data.x86_model >= 0x6 &&

	    boot_cpu_data.x86_model <= 0x7) {

		/* F5x180[19:16]: DF ID */

		ret = get_df_register(misc, 5, 0x180, &value);

		*id = (value >> 16) & 0xf;

drivers/edac/amd64_edac.c

+3 −0
Original line number Diff line number Diff line
@@ -4173,6 +4173,9 @@ static int per_family_init(struct amd64_pvt *pvt) 
		} else if (pvt->model == 0x6) {

			pvt->ctl_name			= "F18h_M06h";

			break;

		} else if (pvt->model == 0x7) {

			pvt->ctl_name			= "F18h_M07h";

			break;

		} else if (pvt->model == 0x10) {

			pvt->ctl_name			= "F18h_M10h";

			break;