Unverified Commit d704f1fe authored Jun 20, 2023 by Arnd Bergmann

Merge tag 'arm-soc/for-6.5/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt

This pull request contains Broadcom ARM64-based SoCs changes for 6.5,
please pull the following:

- Krzysztof fixes the BCMBCA DTS files to have correct cache properties

- Tony unifies the pinctrl-single pin group(s) for the Stingray SoCs

- Aurelien enables the BCM283x DTS files to be built with relocation
  information to make them usable with DT overlays

* tag 'arm-soc/for-6.5/devicetree-arm64' of https://github.com/Broadcom/stblinux:
  arm64: dts: broadcom: Enable device-tree overlay support for RPi devices
  arm64: dts: broadcom: Unify pinctrl-single pin group nodes for stingray
  arm64: dts: broadcom: add missing cache properties

Link: https://lore.kernel.org/r/20230619134920.3384844-2-florian.fainelli@broadcom.com


Signed-off-by: Arnd Bergmann <arnd@arndb.de>

parents 313c22bb 3cdba279

arch/arm64/boot/dts/broadcom/Makefile

+4 −0

Original line number	Diff line number	Diff line
		# SPDX-License-Identifier: GPL-2.0

		# Enables support for device-tree overlays
		DTC_FLAGS := -@

		dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
		bcm2711-rpi-4-b.dtb \
		bcm2711-rpi-cm4-io.dtb \

arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -64,6 +64,7 @@
		l2: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};
		};

arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -52,6 +52,7 @@
		L2_0: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};
		};

arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -36,6 +36,7 @@
		L2_0: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};
		};

arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -52,6 +52,7 @@
		L2_0: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};
		};