Commit d6ef6887 authored by Stanley Chang's avatar Stanley Chang Committed by Greg Kroah-Hartman
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dt-bindings: phy: realtek: Add Realtek DHC RTD SoC USB 3.0 PHY 



Document the USB PHY bindings for Realtek SoCs.
Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB
controller and using USB 3.0 PHY transceiver.

Signed-off-by: default avatarStanley Chang <stanley_chang@realtek.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230725033318.8361-5-stanley_chang@realtek.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 612ad27a

Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright 2023 Realtek Semiconductor Corporation

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/realtek,usb3phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Realtek DHC SoCs USB 3.0 PHY



maintainers:

  - Stanley Chang <stanley_chang@realtek.com>



description: |

  Realtek USB 3.0 PHY support the digital home center (DHC) RTD series SoCs.

  The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs

  support multiple XHCI controllers. One PHY device node maps to one XHCI

  controller.



  RTD1295/RTD1619 SoCs USB

  The USB architecture includes three XHCI controllers.

  Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some

  controllers.

  XHCI controller#0 -- usb2phy -- phy#0

                    |- usb3phy -- phy#0

  XHCI controller#1 -- usb2phy -- phy#0

  XHCI controller#2 -- usb2phy -- phy#0

                    |- usb3phy -- phy#0



  RTD1319/RTD1619b SoCs USB

  The USB architecture includes three XHCI controllers.

  Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2.

  XHCI controller#0 -- usb2phy -- phy#0

  XHCI controller#1 -- usb2phy -- phy#0

  XHCI controller#2 -- usb2phy -- phy#0

                    |- usb3phy -- phy#0



  RTD1319d SoCs USB

  The USB architecture includes three XHCI controllers.

  Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0.

  XHCI controller#0 -- usb2phy -- phy#0

                    |- usb3phy -- phy#0

  XHCI controller#1 -- usb2phy -- phy#0

  XHCI controller#2 -- usb2phy -- phy#0



properties:

  compatible:

    enum:

      - realtek,rtd1295-usb3phy

      - realtek,rtd1319-usb3phy

      - realtek,rtd1319d-usb3phy

      - realtek,rtd1619-usb3phy

      - realtek,rtd1619b-usb3phy



  reg:

    maxItems: 1



  "#phy-cells":

    const: 0



  nvmem-cells:

    maxItems: 1

    description: A phandle to the tx lfps swing trim data provided by

      a nvmem device, if unspecified, default values shall be used.



  nvmem-cell-names:

    items:

      - const: usb_u3_tx_lfps_swing_trim



  realtek,amplitude-control-coarse-tuning:

    description:

      This adjusts the signal amplitude for normal operation and beacon LFPS.

      This value is a parameter for coarse tuning.

      For different boards, if the default value is inappropriate, this

      property can be assigned to adjust.

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 255

    minimum: 0

    maximum: 255



  realtek,amplitude-control-fine-tuning:

    description:

      This adjusts the signal amplitude for normal operation and beacon LFPS.

      This value is used for fine-tuning parameters.

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 65535

    minimum: 0

    maximum: 65535



required:

  - compatible

  - reg

  - "#phy-cells"



additionalProperties: false



examples:

  - |

    usb-phy@13e10 {

        compatible = "realtek,rtd1319d-usb3phy";

        reg = <0x13e10 0x4>;

        #phy-cells = <0>;



        nvmem-cells = <&otp_usb_u3_tx_lfps_swing_trim>;

        nvmem-cell-names = "usb_u3_tx_lfps_swing_trim";



        realtek,amplitude-control-coarse-tuning = <0x77>;

    };