Commit d6e6ac29 authored by Matt Roper's avatar Matt Roper
Browse files

Merge branch 'topic/revid_steppings' into drm-intel-gt-next 



The switch from old old IS_FOO_REVID() macros to the new table-based
IS_FOO_{GT,DISP}_STEP() macros is needed on both drm-intel-next (for
display-based DMC matching) and drm-intel-gt-next (for workaround
guards).  To avoid conflicts, we'll apply the patches to a topic branch
and merge it to both intel branches to ensure the transition to the
new macros is clean.

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
parents 8f88ca76 eee42141

drivers/gpu/drm/i915/display/intel_display_power.c

+1 −1
Original line number Diff line number Diff line
@@ -5798,7 +5798,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) 
	int config, i;



	if (IS_ALDERLAKE_S(dev_priv) ||

	    IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||

	    IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||

	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))

		/* Wa_1409767108:tgl,dg1,adl-s */

		table = wa_1409767108_buddy_page_masks;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+1 −1
Original line number Diff line number Diff line
@@ -2674,7 +2674,7 @@ static bool 
ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)

{

	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&

		 IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||

		 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||

		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&

		 i915->dpll.ref_clks.nssc == 38400;

}

drivers/gpu/drm/i915/display/intel_psr.c

+2 −2
Original line number Diff line number Diff line
@@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 
	if (intel_dp->psr.psr2_sel_fetch_enabled) {

		/* WA 1408330847 */

		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||

		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))

		    IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))

			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,

				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,

				     DIS_RAM_BYPASS_PSR2_MAN_TRACK);
@@ -1221,7 +1221,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) 
	/* WA 1408330847 */

	if (intel_dp->psr.psr2_sel_fetch_enabled &&

	    (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||

	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))

	     IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)))

		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,

			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);

drivers/gpu/drm/i915/gt/intel_region_lmem.c

+1 −1
Original line number Diff line number Diff line
@@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt) 
static bool get_legacy_lowmem_region(struct intel_uncore *uncore,

				     u64 *start, u32 *size)

{

	if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_B0))

	if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))

		return false;



	*start = 0;

drivers/gpu/drm/i915/gt/intel_workarounds.c

+7 −101
Original line number Diff line number Diff line
@@ -514,53 +514,15 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 
		     GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);

}



static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine,

				     struct i915_wa_list *wal)

{

	/* WaForceContextSaveRestoreNonCoherent:cnl */

	wa_masked_en(wal, CNL_HDC_CHICKEN0,

		     HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);



	/* WaDisableReplayBufferBankArbitrationOptimization:cnl */

	wa_masked_en(wal, COMMON_SLICE_CHICKEN2,

		     GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);



	/* WaPushConstantDereferenceHoldDisable:cnl */

	wa_masked_en(wal, GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);



	/* FtrEnableFastAnisoL1BankingFix:cnl */

	wa_masked_en(wal, HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);



	/* WaDisable3DMidCmdPreemption:cnl */

	wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);



	/* WaDisableGPGPUMidCmdPreemption:cnl */

	wa_masked_field_set(wal, GEN8_CS_CHICKEN1,

			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,

			    GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);



	/* WaDisableEarlyEOT:cnl */

	wa_masked_en(wal, GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);

}



static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,

				     struct i915_wa_list *wal)

{

	struct drm_i915_private *i915 = engine->i915;



	/* WaDisableBankHangMode:icl */

	wa_write(wal,

		 GEN8_L3CNTLREG,

		 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |

		 GEN8_ERRDETBCTRL);



	/* Wa_1604370585:icl (pre-prod)

	 * Formerly known as WaPushConstantDereferenceHoldDisable

	 */

	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))

		wa_masked_en(wal, GEN7_ROW_CHICKEN2,

			     PUSH_CONSTANT_DEREF_DISABLE);



	/* WaForceEnableNonCoherent:icl

	 * This is not the same workaround as in early Gen9 platforms, where

	 * lacking this could cause system hangs, but coherency performance
@@ -570,18 +532,6 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 
	 */

	wa_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);



	/* Wa_2006611047:icl (pre-prod)

	 * Formerly known as WaDisableImprovedTdlClkGating

	 */

	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))

		wa_masked_en(wal, GEN7_ROW_CHICKEN2,

			     GEN11_TDL_CLOCK_GATING_FIX_DISABLE);



	/* Wa_2006665173:icl (pre-prod) */

	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))

		wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,

			     GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);



	/* WaEnableFloatBlendOptimization:icl */

	wa_write_clr_set(wal,

			 GEN10_CACHE_MODE_SS,
@@ -711,8 +661,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 
		gen12_ctx_workarounds_init(engine, wal);

	else if (GRAPHICS_VER(i915) == 11)

		icl_ctx_workarounds_init(engine, wal);

	else if (IS_CANNONLAKE(i915))

		cnl_ctx_workarounds_init(engine, wal);

	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))

		cfl_ctx_workarounds_init(engine, wal);

	else if (IS_GEMINILAKE(i915))
@@ -890,7 +838,7 @@ skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 
		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);



	/* WaInPlaceDecompressionHang:skl */

	if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER))

	if (IS_SKL_GT_STEP(i915, STEP_H0, STEP_FOREVER))

		wa_write_or(wal,

			    GEN9_GAMT_ECO_REG_RW_IA,

			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
@@ -989,15 +937,6 @@ icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 
	wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);

}



static void

cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)

{

	/* WaInPlaceDecompressionHang:cnl */

	wa_write_or(wal,

		    GEN9_GAMT_ECO_REG_RW_IA,

		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);

}



static void

icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)

{
@@ -1029,18 +968,6 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 
		    GEN8_GAMW_ECO_DEV_RW_IA,

		    GAMW_ECO_DEV_CTX_RELOAD_DISABLE);



	/* Wa_1405779004:icl (pre-prod) */

	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))

		wa_write_or(wal,

			    SLICE_UNIT_LEVEL_CLKGATE,

			    MSCUNIT_CLKGATE_DIS);



	/* Wa_1406838659:icl (pre-prod) */

	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))

		wa_write_or(wal,

			    INF_UNIT_LEVEL_CLKGATE,

			    CGPSF_CLKGATE_DIS);



	/* Wa_1406463099:icl

	 * Formerly known as WaGamTlbPendError

	 */
@@ -1050,7 +977,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 


	/* Wa_1607087056:icl,ehl,jsl */

	if (IS_ICELAKE(i915) ||

	    IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0))

	    IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))

		wa_write_or(wal,

			    SLICE_UNIT_LEVEL_CLKGATE,

			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1118,7 +1045,7 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 
	gen12_gt_workarounds_init(i915, wal);



	/* Wa_1607087056:dg1 */

	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))

	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))

		wa_write_or(wal,

			    SLICE_UNIT_LEVEL_CLKGATE,

			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1147,8 +1074,6 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) 
		gen12_gt_workarounds_init(i915, wal);

	else if (GRAPHICS_VER(i915) == 11)

		icl_gt_workarounds_init(i915, wal);

	else if (IS_CANNONLAKE(i915))

		cnl_gt_workarounds_init(i915, wal);

	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))

		cfl_gt_workarounds_init(i915, wal);

	else if (IS_GEMINILAKE(i915))
@@ -1425,17 +1350,6 @@ static void cml_whitelist_build(struct intel_engine_cs *engine) 
	cfl_whitelist_build(engine);

}



static void cnl_whitelist_build(struct intel_engine_cs *engine)

{

	struct i915_wa_list *w = &engine->whitelist;



	if (engine->class != RENDER_CLASS)

		return;



	/* WaEnablePreemptionGranularityControlByUMD:cnl */

	whitelist_reg(w, GEN8_CS_CHICKEN1);

}



static void icl_whitelist_build(struct intel_engine_cs *engine)

{

	struct i915_wa_list *w = &engine->whitelist;
@@ -1529,7 +1443,7 @@ static void dg1_whitelist_build(struct intel_engine_cs *engine) 
	tgl_whitelist_build(engine);



	/* GEN:BUG:1409280441:dg1 */

	if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&

	if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&

	    (engine->class == RENDER_CLASS ||

	     engine->class == COPY_ENGINE_CLASS))

		whitelist_reg_ext(w, RING_ID(engine->mmio_base),
@@ -1549,8 +1463,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) 
		tgl_whitelist_build(engine);

	else if (GRAPHICS_VER(i915) == 11)

		icl_whitelist_build(engine);

	else if (IS_CANNONLAKE(i915))

		cnl_whitelist_build(engine);

	else if (IS_COMETLAKE(i915))

		cml_whitelist_build(engine);

	else if (IS_COFFEELAKE(i915))
@@ -1599,7 +1511,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
{

	struct drm_i915_private *i915 = engine->i915;



	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||

	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||

	    IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {

		/*

		 * Wa_1607138336:tgl[a0],dg1[a0]
@@ -1645,7 +1557,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
	}



	if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||

	    IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||

	    IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||

	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {

		/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */

		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
@@ -1659,7 +1571,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
	}





	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||

	if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||

	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {

		/*

		 * Wa_1607030317:tgl
@@ -1732,12 +1644,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
			    PMFLUSH_GAPL3UNBLOCK |

			    PMFLUSHDONE_LNEBLK);



		/* Wa_1406609255:icl (pre-prod) */

		if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))

			wa_write_or(wal,

				    GEN7_SARCHKMD,

				    GEN7_DISABLE_DEMAND_PREFETCH);



		/* Wa_1606682166:icl */

		wa_write_or(wal,

			    GEN7_SARCHKMD,