Loading arch/i386/kernel/cpu/cyrix.c +1 −1 Original line number Diff line number Diff line Loading @@ -354,7 +354,7 @@ static void __init init_nsc(struct cpuinfo_x86 *c) * This function only handles the GX processor, and kicks every * thing else to the Cyrix init function above - that should * cover any processors that might have been branded differently * after NSC aquired Cyrix. * after NSC acquired Cyrix. * * If this breaks your GX1 horribly, please e-mail * info-linux@ldcmail.amd.com to tell us. Loading arch/i386/kernel/i8259.c +1 −1 Original line number Diff line number Diff line Loading @@ -175,7 +175,7 @@ static void mask_and_ack_8259A(unsigned int irq) * Lightweight spurious IRQ detection. We do not want * to overdo spurious IRQ handling - it's usually a sign * of hardware problems, so we only do the checks we can * do without slowing down good hardware unnecesserily. * do without slowing down good hardware unnecessarily. * * Note that IRQ7 and IRQ15 (the two spurious IRQs * usually resulting from the 8259A-1|2 PICs) occur Loading arch/mips/momentum/ocelot_g/gt-irq.c +2 −2 Original line number Diff line number Diff line Loading @@ -59,7 +59,7 @@ void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr) * bit_num - Indicates which bit number in the cause register * * Outputs : * 1 if succesful, 0 if failure * 1 if successful, 0 if failure */ int enable_galileo_irq(int int_cause, int bit_num) { Loading @@ -83,7 +83,7 @@ int enable_galileo_irq(int int_cause, int bit_num) * bit_num - Indicates which bit number in the cause register * * Outputs : * 1 if succesful, 0 if failure * 1 if successful, 0 if failure */ int disable_galileo_irq(int int_cause, int bit_num) { Loading arch/powerpc/platforms/cell/spufs/switch.c +1 −1 Original line number Diff line number Diff line Loading @@ -2100,7 +2100,7 @@ EXPORT_SYMBOL_GPL(spu_save); * @spu: pointer to SPU iomem structure. * * Perform harvest + restore, as we may not be coming * from a previous succesful save operation, and the * from a previous successful save operation, and the * hardware state is unknown. */ int spu_restore(struct spu_state *new, struct spu *spu) Loading arch/powerpc/platforms/pseries/eeh_cache.c +1 −1 Original line number Diff line number Diff line Loading @@ -287,7 +287,7 @@ void pci_addr_cache_remove_device(struct pci_dev *dev) * find the pci device that corresponds to a given address. * This routine scans all pci busses to build the cache. * Must be run late in boot process, after the pci controllers * have been scaned for devices (after all device resources are known). * have been scanned for devices (after all device resources are known). */ void __init pci_addr_cache_build(void) { Loading Loading
arch/i386/kernel/cpu/cyrix.c +1 −1 Original line number Diff line number Diff line Loading @@ -354,7 +354,7 @@ static void __init init_nsc(struct cpuinfo_x86 *c) * This function only handles the GX processor, and kicks every * thing else to the Cyrix init function above - that should * cover any processors that might have been branded differently * after NSC aquired Cyrix. * after NSC acquired Cyrix. * * If this breaks your GX1 horribly, please e-mail * info-linux@ldcmail.amd.com to tell us. Loading
arch/i386/kernel/i8259.c +1 −1 Original line number Diff line number Diff line Loading @@ -175,7 +175,7 @@ static void mask_and_ack_8259A(unsigned int irq) * Lightweight spurious IRQ detection. We do not want * to overdo spurious IRQ handling - it's usually a sign * of hardware problems, so we only do the checks we can * do without slowing down good hardware unnecesserily. * do without slowing down good hardware unnecessarily. * * Note that IRQ7 and IRQ15 (the two spurious IRQs * usually resulting from the 8259A-1|2 PICs) occur Loading
arch/mips/momentum/ocelot_g/gt-irq.c +2 −2 Original line number Diff line number Diff line Loading @@ -59,7 +59,7 @@ void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr) * bit_num - Indicates which bit number in the cause register * * Outputs : * 1 if succesful, 0 if failure * 1 if successful, 0 if failure */ int enable_galileo_irq(int int_cause, int bit_num) { Loading @@ -83,7 +83,7 @@ int enable_galileo_irq(int int_cause, int bit_num) * bit_num - Indicates which bit number in the cause register * * Outputs : * 1 if succesful, 0 if failure * 1 if successful, 0 if failure */ int disable_galileo_irq(int int_cause, int bit_num) { Loading
arch/powerpc/platforms/cell/spufs/switch.c +1 −1 Original line number Diff line number Diff line Loading @@ -2100,7 +2100,7 @@ EXPORT_SYMBOL_GPL(spu_save); * @spu: pointer to SPU iomem structure. * * Perform harvest + restore, as we may not be coming * from a previous succesful save operation, and the * from a previous successful save operation, and the * hardware state is unknown. */ int spu_restore(struct spu_state *new, struct spu *spu) Loading
arch/powerpc/platforms/pseries/eeh_cache.c +1 −1 Original line number Diff line number Diff line Loading @@ -287,7 +287,7 @@ void pci_addr_cache_remove_device(struct pci_dev *dev) * find the pci device that corresponds to a given address. * This routine scans all pci busses to build the cache. * Must be run late in boot process, after the pci controllers * have been scaned for devices (after all device resources are known). * have been scanned for devices (after all device resources are known). */ void __init pci_addr_cache_build(void) { Loading