Loading arch/x86/kvm/emulate.c +5 −2 Original line number Diff line number Diff line Loading @@ -1194,9 +1194,9 @@ x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) break; case DstAcc: c->dst.type = OP_REG; c->dst.bytes = c->op_bytes; c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; c->dst.ptr = &c->regs[VCPU_REGS_RAX]; switch (c->op_bytes) { switch (c->dst.bytes) { case 1: c->dst.val = *(u8 *)c->dst.ptr; break; Loading @@ -1206,6 +1206,9 @@ x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) case 4: c->dst.val = *(u32 *)c->dst.ptr; break; case 8: c->dst.val = *(u64 *)c->dst.ptr; break; } c->dst.orig_val = c->dst.val; break; Loading Loading
arch/x86/kvm/emulate.c +5 −2 Original line number Diff line number Diff line Loading @@ -1194,9 +1194,9 @@ x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) break; case DstAcc: c->dst.type = OP_REG; c->dst.bytes = c->op_bytes; c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; c->dst.ptr = &c->regs[VCPU_REGS_RAX]; switch (c->op_bytes) { switch (c->dst.bytes) { case 1: c->dst.val = *(u8 *)c->dst.ptr; break; Loading @@ -1206,6 +1206,9 @@ x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) case 4: c->dst.val = *(u32 *)c->dst.ptr; break; case 8: c->dst.val = *(u64 *)c->dst.ptr; break; } c->dst.orig_val = c->dst.val; break; Loading