Commit d6b87f25 authored by Sean Christopherson's avatar Sean Christopherson Committed by Paolo Bonzini
Browse files

KVM: x86/mmu: Co-locate code for setting various SPTE masks 



Squish all the code for (re)setting the various SPTE masks into one
location.  With the split code, it's not at all clear that the masks are
set once during module initialization.  This will allow a future patch to
clean up initialization of the masks without shuffling code all over
tarnation.

No functional change intended.

Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
Message-Id: <20210225204749.1512652-17-seanjc@google.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent ec761cfd

arch/x86/kvm/mmu/mmu.c

+0 −25
Original line number Diff line number Diff line
@@ -5754,25 +5754,6 @@ static void mmu_destroy_caches(void) 
	kmem_cache_destroy(mmu_page_header_cache);

}



static void kvm_set_mmio_spte_mask(void)

{

	u64 mask;



	/*

	 * Set a reserved PA bit in MMIO SPTEs to generate page faults with

	 * PFEC.RSVD=1 on MMIO accesses.  64-bit PTEs (PAE, x86-64, and EPT

	 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports

	 * 52-bit physical addresses then there are no reserved PA bits in the

	 * PTEs and so the reserved PA approach must be disabled.

	 */

	if (shadow_phys_bits < 52)

		mask = BIT_ULL(51) | PT_PRESENT_MASK;

	else

		mask = 0;



	kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK);

}



static bool get_nx_auto_mode(void)

{

	/* Return true when CPU has the bug, and mitigations are ON */
@@ -5838,12 +5819,6 @@ int kvm_mmu_module_init(void) 


	kvm_mmu_reset_all_pte_masks();



	kvm_set_mmio_spte_mask();



	kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,

			PT_DIRTY_MASK, PT64_NX_MASK, 0,

			PT_PRESENT_MASK, 0, sme_me_mask);



	pte_list_desc_cache = kmem_cache_create("pte_list_desc",

					    sizeof(struct pte_list_desc),

					    0, SLAB_ACCOUNT, NULL);

arch/x86/kvm/mmu/spte.c

+19 −0
Original line number Diff line number Diff line
@@ -310,6 +310,7 @@ EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); 
void kvm_mmu_reset_all_pte_masks(void)

{

	u8 low_phys_bits;

	u64 mask;



	shadow_user_mask = 0;

	shadow_accessed_mask = 0;
@@ -344,4 +345,22 @@ void kvm_mmu_reset_all_pte_masks(void) 


	shadow_nonpresent_or_rsvd_lower_gfn_mask =

		GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);



	/*

	 * Set a reserved PA bit in MMIO SPTEs to generate page faults with

	 * PFEC.RSVD=1 on MMIO accesses.  64-bit PTEs (PAE, x86-64, and EPT

	 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports

	 * 52-bit physical addresses then there are no reserved PA bits in the

	 * PTEs and so the reserved PA approach must be disabled.

	 */

	if (shadow_phys_bits < 52)

		mask = BIT_ULL(51) | PT_PRESENT_MASK;

	else

		mask = 0;



	kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK);



	kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,

			PT_DIRTY_MASK, PT64_NX_MASK, 0,

			PT_PRESENT_MASK, 0, sme_me_mask);

}

arch/x86/kvm/vmx/vmx.c

+6 −11
Original line number Diff line number Diff line
@@ -4314,16 +4314,6 @@ static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 
	vmx->secondary_exec_control = exec_control;

}



static void ept_set_mmio_spte_mask(void)

{

	/*

	 * EPT Misconfigurations can be generated if the value of bits 2:0

	 * of an EPT paging-structure entry is 110b (write/execute).

	 */

	kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE,

				   VMX_EPT_RWX_MASK, 0);

}



#define VMX_XSS_EXIT_BITMAP 0



/*
@@ -5462,7 +5452,12 @@ static void vmx_enable_tdp(void) 
		cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,

		VMX_EPT_RWX_MASK, 0ull);



	ept_set_mmio_spte_mask();

	/*

	 * EPT Misconfigurations can be generated if the value of bits 2:0

	 * of an EPT paging-structure entry is 110b (write/execute).

	 */

	kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE,

				   VMX_EPT_RWX_MASK, 0);

}



/*