Commit d69d5649 authored by Mark Brown's avatar Mark Brown Committed by Will Deacon
Browse files

arm64/sme: Expose SMIDR through sysfs 



We currently expose MIDR and REVID to userspace through sysfs to enable it
to make decisions based on the specific implementation. Since SME supports
implementations where streaming mode is provided by a separate hardware
unit called a SMCU it provides a similar ID register SMIDR. Expose it to
userspace via sysfs when the system supports SME along with the other ID
registers.

Since we disable the SME priority mapping feature if it is supported by
hardware we currently mask out the SMPS bit which reports that it is
supported.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220607132857.1358361-1-broonie@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent a111daf0

Documentation/ABI/testing/sysfs-devices-system-cpu

+2 −1
Original line number Original line Diff line number Diff line
@@ -493,12 +493,13 @@ What: /sys/devices/system/cpu/cpuX/regs/ 
		/sys/devices/system/cpu/cpuX/regs/identification/

		/sys/devices/system/cpu/cpuX/regs/identification/

		/sys/devices/system/cpu/cpuX/regs/identification/midr_el1

		/sys/devices/system/cpu/cpuX/regs/identification/midr_el1

		/sys/devices/system/cpu/cpuX/regs/identification/revidr_el1

		/sys/devices/system/cpu/cpuX/regs/identification/revidr_el1

		/sys/devices/system/cpu/cpuX/regs/identification/smidr_el1

Date:		June 2016

Date:		June 2016

Contact:	Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>

Contact:	Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>

Description:	AArch64 CPU registers

Description:	AArch64 CPU registers





		'identification' directory exposes the CPU ID registers for

		'identification' directory exposes the CPU ID registers for

		identifying model and revision of the CPU.

		identifying model and revision of the CPU and SMCU.





What:		/sys/devices/system/cpu/aarch32_el0

What:		/sys/devices/system/cpu/aarch32_el0

Date:		May 2021

Date:		May 2021

arch/arm64/include/asm/cpu.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -46,6 +46,7 @@ struct cpuinfo_arm64 { 
	u64		reg_midr;

	u64		reg_midr;

	u64		reg_revidr;

	u64		reg_revidr;

	u64		reg_gmid;

	u64		reg_gmid;

	u64		reg_smidr;





	u64		reg_id_aa64dfr0;

	u64		reg_id_aa64dfr0;

	u64		reg_id_aa64dfr1;

	u64		reg_id_aa64dfr1;

arch/arm64/kernel/cpuinfo.c

+22 −1
Original line number Original line Diff line number Diff line
@@ -267,6 +267,7 @@ static struct kobj_type cpuregs_kobj_type = { 




CPUREGS_ATTR_RO(midr_el1, midr);

CPUREGS_ATTR_RO(midr_el1, midr);

CPUREGS_ATTR_RO(revidr_el1, revidr);

CPUREGS_ATTR_RO(revidr_el1, revidr);

CPUREGS_ATTR_RO(smidr_el1, smidr);





static struct attribute *cpuregs_id_attrs[] = {

static struct attribute *cpuregs_id_attrs[] = {

	&cpuregs_attr_midr_el1.attr,

	&cpuregs_attr_midr_el1.attr,
@@ -279,6 +280,16 @@ static const struct attribute_group cpuregs_attr_group = { 
	.name = "identification"

	.name = "identification"

};

};





static struct attribute *sme_cpuregs_id_attrs[] = {

	&cpuregs_attr_smidr_el1.attr,

	NULL

};



static const struct attribute_group sme_cpuregs_attr_group = {

	.attrs = sme_cpuregs_id_attrs,

	.name = "identification"

};



static int cpuid_cpu_online(unsigned int cpu)

static int cpuid_cpu_online(unsigned int cpu)

{

{

	int rc;

	int rc;
@@ -296,6 +307,8 @@ static int cpuid_cpu_online(unsigned int cpu) 
	rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);

	rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);

	if (rc)

	if (rc)

		kobject_del(&info->kobj);

		kobject_del(&info->kobj);

	if (system_supports_sme())

		rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group);

out:

out:

	return rc;

	return rc;

}

}
@@ -423,9 +436,17 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
		info->reg_zcr = read_zcr_features();

		info->reg_zcr = read_zcr_features();





	if (IS_ENABLED(CONFIG_ARM64_SME) &&

	if (IS_ENABLED(CONFIG_ARM64_SME) &&

	    id_aa64pfr1_sme(info->reg_id_aa64pfr1))

	    id_aa64pfr1_sme(info->reg_id_aa64pfr1)) {

		info->reg_smcr = read_smcr_features();

		info->reg_smcr = read_smcr_features();





		/*

		 * We mask out SMPS since even if the hardware

		 * supports priorities the kernel does not at present

		 * and we block access to them.

		 */

		info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;

	}



	cpuinfo_detect_icache_policy(info);

	cpuinfo_detect_icache_policy(info);

}

}