Commit d66a8aab authored by Vadim Pasternak's avatar Vadim Pasternak Committed by Hans de Goede
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platform: mellanox: Change register offset addresses 



Move debug register offsets to different location due to hardware changes.

Fixes: dd635e33 ("platform: mellanox: Introduce support of new Nvidia L1 switch")
Signed-off-by: default avatarVadim Pasternak <vadimp@nvidia.com>
Reviewed-by: default avatarMichael Shych <michaelsh@nvidia.com>
Link: https://lore.kernel.org/r/20230813083735.39090-5-vadimp@nvidia.com


Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 9f8ccdb5

drivers/platform/x86/mlx-platform.c

+4 −4
Original line number Diff line number Diff line
@@ -62,10 +62,6 @@ 
#define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET	0x37

#define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET	0x3a

#define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET	0x3b

#define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET	0x3c

#define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET	0x3d

#define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET	0x3e

#define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET	0x3f

#define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET	0x40

#define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET	0x41

#define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET	0x42
@@ -126,6 +122,10 @@ 
#define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET	0xaa

#define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET	0xab

#define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON		0xb2

#define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET	0xb6

#define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET	0xb7

#define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET	0xb8

#define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET	0xb9

#define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET	0xc2

#define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT	0xc3

#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET	0xc7