Commit d6683bbe authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/xelpmp: Consider GSI offset when doing MCR lookups 



MCR range tables use the final MMIO offset of a register (including the
0x380000 GSI offset when applicable).  Since the i915_mcr_reg_t passed
as a parameter during steering lookup does not include the GSI offset,
we need to add it back in for GSI registers before searching the tables.

Fixes: a7ec65fc ("drm/i915/xelpmp: Add multicast steering for media GT")
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230214001906.1477370-1-matthew.d.roper@intel.com
parent 4583d6be

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

+4 −1
Original line number Diff line number Diff line
@@ -561,12 +561,15 @@ static bool reg_needs_read_steering(struct intel_gt *gt, 
				    i915_mcr_reg_t reg,

				    enum intel_steering_type type)

{

	const u32 offset = i915_mmio_reg_offset(reg);

	u32 offset = i915_mmio_reg_offset(reg);

	const struct intel_mmio_range *entry;



	if (likely(!gt->steering_table[type]))

		return false;



	if (IS_GSI_REG(offset))

		offset += gt->uncore->gsi_offset;



	for (entry = gt->steering_table[type]; entry->end; entry++) {

		if (offset >= entry->start && offset <= entry->end)

			return true;