Commit d63e1c76 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Stephen Boyd
Browse files

clk: qcom: gcc-sdm845: get rid of the test clock 



The test clock isn't in the bindings and apparently it's not used by
anyone upstream.  Remove it.

Suggested-by: default avatarStephen Boyd <swboyd@chromium.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210409183004.1617777-4-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent ea434d7a

drivers/clk/qcom/gcc-sdm845.c

+0 −15
Original line number Diff line number Diff line
@@ -28,7 +28,6 @@ 
enum {

	P_BI_TCXO,

	P_AUD_REF_CLK,

	P_CORE_BI_PLL_TEST_SE,

	P_GPLL0_OUT_EVEN,

	P_GPLL0_OUT_MAIN,

	P_GPLL4_OUT_MAIN,
@@ -98,14 +97,12 @@ static const struct parent_map gcc_parent_map_0[] = { 
	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gcc_parent_data_0[] = {

	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },

	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct parent_map gcc_parent_map_1[] = {
@@ -113,7 +110,6 @@ static const struct parent_map gcc_parent_map_1[] = { 
	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_SLEEP_CLK, 5 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gcc_parent_data_1[] = {
@@ -121,41 +117,34 @@ static const struct clk_parent_data gcc_parent_data_1[] = { 
	{ .hw = &gpll0.clkr.hw },

	{ .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct parent_map gcc_parent_map_2[] = {

	{ P_BI_TCXO, 0 },

	{ P_SLEEP_CLK, 5 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gcc_parent_data_2[] = {

	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },

	{ .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct parent_map gcc_parent_map_3[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gcc_parent_data_3[] = {

	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },

	{ .hw = &gpll0.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct parent_map gcc_parent_map_4[] = {

	{ P_BI_TCXO, 0 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gcc_parent_data_4[] = {

	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct parent_map gcc_parent_map_6[] = {
@@ -163,7 +152,6 @@ static const struct parent_map gcc_parent_map_6[] = { 
	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_AUD_REF_CLK, 2 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gcc_parent_data_6[] = {
@@ -171,7 +159,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = { 
	{ .hw = &gpll0.clkr.hw },

	{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};



static const struct clk_parent_data gcc_parent_data_7_ao[] = {
@@ -198,7 +185,6 @@ static const struct parent_map gcc_parent_map_10[] = { 
	{ P_GPLL0_OUT_MAIN, 1 },

	{ P_GPLL4_OUT_MAIN, 5 },

	{ P_GPLL0_OUT_EVEN, 6 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data gcc_parent_data_10[] = {
@@ -206,7 +192,6 @@ static const struct clk_parent_data gcc_parent_data_10[] = { 
	{ .hw = &gpll0.clkr.hw },

	{ .hw = &gpll4.clkr.hw },

	{ .hw = &gpll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },

};