Commit d5e0fb0d authored by George Shen's avatar George Shen Committed by Alex Deucher
Browse files

drm/amd/display: Add DSC delay factor workaround 



[Why]
Certain 4K high refresh rate modes requiring DSC are exhibiting top
of screen underflow corruption. Increasing the DSC delay by a factor
of 6 percent stops the underflow for most use cases.

[How]
Multiply DSC delay requirement in DML by a factor.
Add debug option to make this DSC delay factor configurable.

Reviewed-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarGeorge Shen <george.shen@amd.com>
Tested-by: default avatarMark Broadworth <mark.broadworth@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8dc32313

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -852,6 +852,7 @@ struct dc_debug_options { 
	bool enable_double_buffered_dsc_pg_support;

	bool enable_dp_dig_pixel_rate_div_policy;

	enum lttpr_mode lttpr_mode_override;

	unsigned int dsc_delay_factor_wa_x1000;

};



struct gpu_info_soc_bounding_box_v1_0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+3 −1
Original line number Diff line number Diff line
@@ -2359,9 +2359,11 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa 


		if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)

			dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;



	}



	/* DML DSC delay factor workaround */

	dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;



	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */

	dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

+3 −2
Original line number Diff line number Diff line
@@ -367,7 +367,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman 
				mode_lib->vba.OutputBpp[k], mode_lib->vba.HActive[k], mode_lib->vba.HTotal[k],

				mode_lib->vba.NumberOfDSCSlices[k], mode_lib->vba.OutputFormat[k],

				mode_lib->vba.Output[k], mode_lib->vba.PixelClock[k],

				mode_lib->vba.PixelClockBackEnd[k]);

				mode_lib->vba.PixelClockBackEnd[k], mode_lib->vba.ip.dsc_delay_factor_wa);

	}



	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
@@ -2475,7 +2475,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
					mode_lib->vba.OutputBppPerState[i][k], mode_lib->vba.HActive[k],

					mode_lib->vba.HTotal[k], mode_lib->vba.NumberOfDSCSlices[k],

					mode_lib->vba.OutputFormat[k], mode_lib->vba.Output[k],

					mode_lib->vba.PixelClock[k], mode_lib->vba.PixelClockBackEnd[k]);

					mode_lib->vba.PixelClock[k], mode_lib->vba.PixelClockBackEnd[k],

					mode_lib->vba.ip.dsc_delay_factor_wa);

		}



		for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

+3 −2
Original line number Diff line number Diff line
@@ -1726,7 +1726,8 @@ unsigned int dml32_DSCDelayRequirement(bool DSCEnabled, 
		enum output_format_class  OutputFormat,

		enum output_encoder_class Output,

		double PixelClock,

		double PixelClockBackEnd)

		double PixelClockBackEnd,

		double dsc_delay_factor_wa)

{

	unsigned int DSCDelayRequirement_val;
@@ -1764,7 +1765,7 @@ unsigned int dml32_DSCDelayRequirement(bool DSCEnabled, 
	dml_print("DML::%s: DSCDelayRequirement_val = %d\n", __func__, DSCDelayRequirement_val);

#endif



	return DSCDelayRequirement_val;

	return dml_ceil(DSCDelayRequirement_val * dsc_delay_factor_wa, 1);

}



void dml32_CalculateSurfaceSizeInMall(

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h

+2 −1
Original line number Diff line number Diff line
@@ -327,7 +327,8 @@ unsigned int dml32_DSCDelayRequirement(bool DSCEnabled, 
		enum output_format_class  OutputFormat,

		enum output_encoder_class Output,

		double PixelClock,

		double PixelClockBackEnd);

		double PixelClockBackEnd,

		double dsc_delay_factor_wa);



void dml32_CalculateSurfaceSizeInMall(

		unsigned int NumberOfActiveSurfaces,