Commit d5c421d2 authored by Michal Simek's avatar Michal Simek
Browse files

dt-bindings: xilinx: Switch xilinx.com emails to amd.com 



@xilinx.com is still working but better to switch to new amd.com after
AMD/Xilinx acquisition.

Acked-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C
Acked-by: default avatarMark Brown <broonie@kernel.org>
Acked-by: default avatarJassi Brar <jassisinghbrar@gmail.com>
Acked-by: default avatarDamien Le Moal <dlemoal@kernel.org>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f5b2bd1e78407e4128fc8f0b5874ba723e710a88.1684245058.git.michal.simek@amd.com
parent 45fe0dc4

Documentation/devicetree/bindings/arm/xilinx.yaml

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Xilinx Zynq Platforms



maintainers:

  - Michal Simek <michal.simek@xilinx.com>

  - Michal Simek <michal.simek@amd.com>



description: |

  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC

Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Ceva AHCI SATA Controller



maintainers:

  - Piyush Mehta <piyush.mehta@xilinx.com>

  - Piyush Mehta <piyush.mehta@amd.com>



description: |

  The Ceva SATA controller mostly conforms to the AHCI interface with some

Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Xilinx clocking wizard



maintainers:

  - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>

  - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>



description:

  The clocking wizard is a soft ip clocking block of Xilinx versal. It

Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Xilinx Versal clock controller



maintainers:

  - Michal Simek <michal.simek@xilinx.com>

  - Michal Simek <michal.simek@amd.com>

  - Jolly Shah <jolly.shah@xilinx.com>

  - Rajan Vaja <rajan.vaja@xilinx.com>

Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml

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@@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Xilinx ZynqMP AES-GCM Hardware Accelerator



maintainers:

  - Kalyani Akula <kalyani.akula@xilinx.com>

  - Michal Simek <michal.simek@xilinx.com>

  - Kalyani Akula <kalyani.akula@amd.com>

  - Michal Simek <michal.simek@amd.com>



description: |

  The ZynqMP AES-GCM hardened cryptographic accelerator is used to