Commit d59fa576 authored by Hsin-Yi Wang's avatar Hsin-Yi Wang Committed by sanglipeng
Browse files

mtd: spi-nor: Check bus width while setting QE bit 

stable inclusion
from stable-v5.10.195
commit 40d8f9bffed068b9b5f5ccd7bdf64984435a7110
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I95JOC

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=40d8f9bffed068b9b5f5ccd7bdf64984435a7110



--------------------------------

[ Upstream commit f01d8155 ]

spi_nor_write_16bit_sr_and_check() should also check if bus width is
4 before setting QE bit.

Fixes: 39d1e334 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()")
Suggested-by: default avatarMichael Walle <michael@walle.cc>
Suggested-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: default avatarHsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: default avatarMichael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20230818064524.1229100-2-hsinyi@chromium.org


Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarsanglipeng <sanglipeng1@jd.com>
parent d183c854

drivers/mtd/spi-nor/core.c

+10 −9
Original line number Diff line number Diff line
@@ -800,21 +800,22 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) 
		ret = spi_nor_read_cr(nor, &sr_cr[1]);

		if (ret)

			return ret;

	} else if (nor->params->quad_enable) {

	} else if (spi_nor_get_protocol_width(nor->read_proto) == 4 &&

		   spi_nor_get_protocol_width(nor->write_proto) == 4 &&

		   nor->params->quad_enable) {

		/*

		 * If the Status Register 2 Read command (35h) is not

		 * supported, we should at least be sure we don't

		 * change the value of the SR2 Quad Enable bit.

		 *

		 * We can safely assume that when the Quad Enable method is

		 * set, the value of the QE bit is one, as a consequence of the

		 * nor->params->quad_enable() call.

		 * When the Quad Enable method is set and the buswidth is 4, we

		 * can safely assume that the value of the QE bit is one, as a

		 * consequence of the nor->params->quad_enable() call.

		 *

		 * We can safely assume that the Quad Enable bit is present in

		 * the Status Register 2 at BIT(1). According to the JESD216

		 * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit

		 * Write Status (01h) command is available just for the cases

		 * in which the QE bit is described in SR2 at BIT(1).

		 * According to the JESD216 revB standard, BFPT DWORDS[15],

		 * bits 22:20, the 16-bit Write Status (01h) command is

		 * available just for the cases in which the QE bit is

		 * described in SR2 at BIT(1).

		 */

		sr_cr[1] = SR2_QUAD_EN_BIT1;

	} else {