Unverified Commit d5935537 authored Aug 12, 2021 by Kefeng Wang Committed by Palmer Dabbelt Sep 10, 2021

riscv: Improve stack randomisation on RV64



This enlarges the bits availiable for stack randomisation on RV64 from
the default of 8MiB to 1GiB, to match arm64 and x86.

Also, update the documentation to reflect our support for stack
randomisation.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
[Palmer: commit text]
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

parent efe1e08b

Documentation/features/vm/ELF-ASLR/arch-support.txt

+1 −1

Original line number	Diff line number	Diff line
		@@ -22,7 +22,7 @@
		\| openrisc: \| TODO \|
		\| parisc: \| ok \|
		\| powerpc: \| ok \|
		\| riscv: \| TODO \|
		\| riscv: \| ok \|
		\| s390: \| ok \|
		\| sh: \| TODO \|
		\| sparc: \| TODO \|

arch/riscv/include/asm/elf.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -42,6 +42,9 @@
		*/
		#define ELF_ET_DYN_BASE ((TASK_SIZE / 3) * 2)

		#ifdef CONFIG_64BIT
		#define STACK_RND_MASK (0x3ffff >> (PAGE_SHIFT - 12))
		#endif
		/*
		* This yields a mask that user programs can use to figure out what
		* instruction set this CPU supports. This could be done in user space,