Commit d56aeb21 authored by Xiongfeng Wang's avatar Xiongfeng Wang
Browse files

PCI: Add MCFG quirks for some Hisilicon Chip host controllers 

euler inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I8XW6J


CVE: NA

-------------------------------------------------

The PCIe controller in some Hisilicon Chip is not completely ECAM-compliant.
Part of its PCIe cores do not support ECAM.

Signed-off-by: default avatarXiongfeng Wang <wangxiongfeng2@huawei.com>
Reviewed-by: default avatarKefeng Wang <wangkefeng.wang@huawei.com>
parent 652b917c

drivers/acpi/pci_mcfg.c

+4 −0
Original line number Diff line number Diff line
@@ -79,6 +79,10 @@ static struct mcfg_fixup mcfg_quirks[] = { 
	HISI_QUAD_DOM("HIP07   ",  4, &hisi_pcie_ops),

	HISI_QUAD_DOM("HIP07   ",  8, &hisi_pcie_ops),

	HISI_QUAD_DOM("HIP07   ", 12, &hisi_pcie_ops),

	HISI_QUAD_DOM("HIP12   ", 0x20, &hisi_pcie_ops),

	HISI_QUAD_DOM("HIP12   ", 0x24, &hisi_pcie_ops),

	HISI_QUAD_DOM("HIP12   ", 0x28, &hisi_pcie_ops),

	HISI_QUAD_DOM("HIP12   ", 0x2c, &hisi_pcie_ops),



#define THUNDER_PEM_RES(addr, node) \

	DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)