Commit d5399f11 authored by Mordechay Goodstein's avatar Mordechay Goodstein Committed by Luca Coelho
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iwlwifi: cfg: add support for 1K BA queue



In order to support 1K aggregations start ba queue with at least double
the size, also allocate based on the connecting type to save memory
usage.

Signed-off-by: default avatarMordechay Goodstein <mordechay.goodstein@intel.com>
Signed-off-by: default avatarLuca Coelho <luciano.coelho@intel.com>
Link: https://lore.kernel.org/r/iwlwifi.20220128153014.16b43fe3e92f.I853c57648feee4b69ccb01ef4c75354377d60be2@changeid


Signed-off-by: default avatarLuca Coelho <luciano.coelho@intel.com>
parent 3827cb59
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+3 −2
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@@ -7,6 +7,7 @@
#include <linux/stringify.h>
#include "iwl-config.h"
#include "iwl-prph.h"
#include "fw/api/txq.h"

/* Highest firmware API version supported */
#define IWL_22000_UCODE_API_MAX	69
@@ -224,7 +225,7 @@ static const struct iwl_ht_params iwl_22000_ht_params = {
	.trans.base_params = &iwl_ax210_base_params,			\
	.min_txq_size = 128,						\
	.gp2_reg_addr = 0xd02c68,					\
	.min_256_ba_txq_size = 1024,					\
	.min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE,		\
	.mon_dram_regs = {						\
		.write_ptr = {						\
			.addr = DBGC_CUR_DBGBUF_STATUS,			\
@@ -285,7 +286,7 @@ static const struct iwl_ht_params iwl_22000_ht_params = {
	.trans.base_params = &iwl_ax210_base_params,			\
	.min_txq_size = 128,						\
	.gp2_reg_addr = 0xd02c68,					\
	.min_256_ba_txq_size = 1024,					\
	.min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT,		\
	.mon_dram_regs = {						\
		.write_ptr = {						\
			.addr = DBGC_CUR_DBGBUF_STATUS,			\
+3 −1
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
 * Copyright (C) 2005-2014, 2019-2020 Intel Corporation
 * Copyright (C) 2005-2014, 2019-2021 Intel Corporation
 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
 * Copyright (C) 2016-2017 Intel Deutschland GmbH
 */
@@ -76,6 +76,8 @@ enum iwl_tx_queue_cfg_actions {
	TX_QUEUE_CFG_TFD_SHORT_FORMAT		= BIT(1),
};

#define IWL_DEFAULT_QUEUE_SIZE_EHT (1024 * 4)
#define IWL_DEFAULT_QUEUE_SIZE_HE 1024
#define IWL_DEFAULT_QUEUE_SIZE 256
#define IWL_MGMT_QUEUE_SIZE 16
#define IWL_CMD_QUEUE_SIZE 32
+3 −3
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@@ -343,8 +343,8 @@ struct iwl_fw_mon_regs {
 * @bisr_workaround: BISR hardware workaround (for 22260 series devices)
 * @min_txq_size: minimum number of slots required in a TX queue
 * @uhb_supported: ultra high band channels supported
 * @min_256_ba_txq_size: minimum number of slots required in a TX queue which
 *	supports 256 BA aggregation
 * @min_ba_txq_size: minimum number of slots required in a TX queue which
 *	based on hardware support (HE - 256, EHT - 1K).
 * @num_rbds: number of receive buffer descriptors to use
 *	(only used for multi-queue capable devices)
 * @mac_addr_csr_base: CSR base register for MAC address access, if not set
@@ -405,7 +405,7 @@ struct iwl_cfg {
	u32 d3_debug_data_length;
	u32 min_txq_size;
	u32 gp2_reg_addr;
	u32 min_256_ba_txq_size;
	u32 min_ba_txq_size;
	const struct iwl_fw_mon_regs mon_dram_regs;
	const struct iwl_fw_mon_regs mon_smem_regs;
};
+6 −5
Original line number Diff line number Diff line
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
 * Copyright (C) 2005-2014, 2018-2020 Intel Corporation
 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation
 * Copyright (C) 2015-2017 Intel Deutschland GmbH
 */
#ifndef __iwl_fh_h__
@@ -590,7 +590,8 @@ struct iwl_rb_status {
#define TFD_QUEUE_CB_SIZE(x)	(ilog2(x) - 3)
#define TFD_QUEUE_SIZE_BC_DUP	(64)
#define TFD_QUEUE_BC_SIZE	(TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
#define TFD_QUEUE_BC_SIZE_GEN3	1024
#define TFD_QUEUE_BC_SIZE_GEN3_AX210	1024
#define TFD_QUEUE_BC_SIZE_GEN3_BZ	(1024 * 4)
#define IWL_TX_DMA_MASK        DMA_BIT_MASK(36)
#define IWL_NUM_OF_TBS		20
#define IWL_TFH_NUM_TBS		25
@@ -707,14 +708,14 @@ struct iwlagn_scd_bc_tbl {
} __packed;

/**
 * struct iwl_gen3_bc_tbl scheduler byte count table gen3
 * struct iwl_gen3_bc_tbl_entry scheduler byte count table entry gen3
 * For AX210 and on:
 * @tfd_offset: 0-12 - tx command byte count
 *		12-13 - number of 64 byte chunks
 *		14-16 - reserved
 */
struct iwl_gen3_bc_tbl {
	__le16 tfd_offset[TFD_QUEUE_BC_SIZE_GEN3];
struct iwl_gen3_bc_tbl_entry {
	__le16 tfd_offset;
} __packed;

#endif /* !__iwl_fh_h__ */
+6 −2
Original line number Diff line number Diff line
@@ -78,8 +78,12 @@ int iwl_trans_init(struct iwl_trans *trans)
	if (WARN_ON(trans->trans_cfg->gen2 && txcmd_size >= txcmd_align))
		return -EINVAL;

	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
		trans->txqs.bc_tbl_size = sizeof(struct iwl_gen3_bc_tbl);
	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
		trans->txqs.bc_tbl_size =
			sizeof(struct iwl_gen3_bc_tbl_entry) * TFD_QUEUE_BC_SIZE_GEN3_BZ;
	else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
		trans->txqs.bc_tbl_size =
			sizeof(struct iwl_gen3_bc_tbl_entry) * TFD_QUEUE_BC_SIZE_GEN3_AX210;
	else
		trans->txqs.bc_tbl_size = sizeof(struct iwlagn_scd_bc_tbl);
	/*
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