Commit d51f86cf authored by Alexey Kardashevskiy's avatar Alexey Kardashevskiy Committed by Michael Ellerman
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powerpc/mm: Switch obsolete dssall to .long 



The dssall ("Data Stream Stop All") instruction is obsolete altogether
with other Data Cache Instructions since ISA 2.03 (year 2006).

LLVM IAS does not support it but PPC970 seems to be using it.
This switches dssall to .long as there is no much point in fixing LLVM.

Signed-off-by: default avatarAlexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211221055904.555763-6-aik@ozlabs.ru
parent d72c4a36

arch/powerpc/include/asm/ppc-opcode.h

+2 −0
Original line number Diff line number Diff line
@@ -249,6 +249,7 @@ 
#define PPC_INST_COPY			0x7c20060c

#define PPC_INST_DCBA			0x7c0005ec

#define PPC_INST_DCBA_MASK		0xfc0007fe

#define PPC_INST_DSSALL			0x7e00066c

#define PPC_INST_ISEL			0x7c00001e

#define PPC_INST_ISEL_MASK		0xfc00003e

#define PPC_INST_LSWI			0x7c0004aa
@@ -577,6 +578,7 @@ 
#define	PPC_DCBZL(a, b)		stringify_in_c(.long PPC_RAW_DCBZL(a, b))

#define	PPC_DIVDE(t, a, b)	stringify_in_c(.long PPC_RAW_DIVDE(t, a, b))

#define	PPC_DIVDEU(t, a, b)	stringify_in_c(.long PPC_RAW_DIVDEU(t, a, b))

#define PPC_DSSALL		stringify_in_c(.long PPC_INST_DSSALL)

#define PPC_LQARX(t, a, b, eh)	stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh))

#define PPC_STQCX(t, a, b)	stringify_in_c(.long PPC_RAW_STQCX(t, a, b))

#define PPC_MADDHD(t, a, b, c)	stringify_in_c(.long PPC_RAW_MADDHD(t, a, b, c))

arch/powerpc/kernel/idle.c

+1 −1
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ void power4_idle(void) 
		return;



	if (cpu_has_feature(CPU_FTR_ALTIVEC))

		asm volatile("DSSALL ; sync" ::: "memory");

		asm volatile(PPC_DSSALL " ; sync" ::: "memory");



	power4_idle_nap();

arch/powerpc/kernel/idle_6xx.S

+1 −1
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ BEGIN_FTR_SECTION 
END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)

	mtspr	SPRN_HID0,r4

BEGIN_FTR_SECTION

	DSSALL

	PPC_DSSALL

	sync

END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)

	lwz	r8,TI_LOCAL_FLAGS(r2)	/* set napping bit */

arch/powerpc/kernel/l2cr_6xx.S

+3 −3
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_L2CR) 


	/* Stop DST streams */

BEGIN_FTR_SECTION

	DSSALL

	PPC_DSSALL

	sync

END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
@@ -292,7 +292,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_L3CR) 
	isync



	/* Stop DST streams */

	DSSALL

	PPC_DSSALL

	sync



	/* Get the current enable bit of the L3CR into r4 */
@@ -401,7 +401,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_L3CR) 
_GLOBAL(__flush_disable_L1)

	/* Stop pending alitvec streams and memory accesses */

BEGIN_FTR_SECTION

	DSSALL

	PPC_DSSALL

END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)

 	sync

arch/powerpc/kernel/swsusp_32.S

+1 −1
Original line number Diff line number Diff line
@@ -181,7 +181,7 @@ _GLOBAL(swsusp_arch_resume) 
#ifdef CONFIG_ALTIVEC

	/* Stop pending alitvec streams and memory accesses */

BEGIN_FTR_SECTION

	DSSALL

	PPC_DSSALL

END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)

#endif

 	sync