Commit d5065050 authored by Richard Zhu's avatar Richard Zhu Committed by Shawn Guo
Browse files

arm64: dts: imx8mp-evk: Add PCIe support 



Add PCIe support on i.MX8MP EVK board.

Signed-off-by: default avatarRichard Zhu <hongxing.zhu@nxp.com>
Tested-by: default avatarMarek Vasut <marex@denx.de>
Tested-by: default avatarRichard Leitner <richard.leitner@skidata.com>
Tested-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 9e65987b

arch/arm64/boot/dts/freescale/imx8mp-evk.dts

+53 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 


/dts-v1/;



#include <dt-bindings/phy/phy-imx8-pcie.h>

#include "imx8mp.dtsi"



/ {
@@ -33,6 +34,12 @@ 
		      <0x1 0x00000000 0 0xc0000000>;

	};



	pcie0_refclk: pcie0-refclk {

		compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <100000000>;

	};



	reg_can1_stby: regulator-can1-stby {

		compatible = "regulator-fixed";

		regulator-name = "can1-stby";
@@ -55,6 +62,17 @@ 
		enable-active-high;

	};



	reg_pcie0: regulator-pcie {

		compatible = "regulator-fixed";

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_pcie0_reg>;

		regulator-name = "MPCIE_3V3";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};



	reg_usdhc2_vmmc: regulator-usdhc2 {

		compatible = "regulator-fixed";

		pinctrl-names = "default";
@@ -350,6 +368,28 @@ 
	 */

};



&pcie_phy {

	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;

	clocks = <&pcie0_refclk>;

	clock-names = "ref";

	status = "okay";

};



&pcie {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,

		 <&clk IMX8MP_CLK_PCIE_ROOT>,

		 <&clk IMX8MP_CLK_HSIO_AXI>;

	clock-names = "pcie", "pcie_aux", "pcie_bus";

	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;

	assigned-clock-rates = <10000000>;

	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;

	vpcie-supply = <&reg_pcie0>;

	status = "okay";

};



&snvs_pwrkey {

	status = "okay";

};
@@ -502,6 +542,19 @@ 
		>;

	};



	pinctrl_pcie0: pcie0grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x61 /* open drain, pull up */

			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x41

		>;

	};



	pinctrl_pcie0_reg: pcie0reggrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x41

		>;

	};



	pinctrl_pmic: pmicgrp {

		fsl,pins = <

			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x000001c0