dt-bindings: fpga: convert Xilinx Zynq MPSoC bindings to YAML

Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.

The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the

Programmable Logic (PL). The configuration uses  the firmware interface.

Required properties:

- compatible: should contain "xlnx,zynqmp-pcap-fpga"

Example for full FPGA configuration:

	fpga-region0 {

		compatible = "fpga-region";

		fpga-mgr = <&zynqmp_pcap>;

		#address-cells = <0x1>;

		#size-cells = <0x1>;

	};

	firmware {

		zynqmp_firmware: zynqmp-firmware {

			compatible = "xlnx,zynqmp-firmware";

			method = "smc";

			zynqmp_pcap: pcap {

				compatible = "xlnx,zynqmp-pcap-fpga";

			};

		};

	};

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Zynq Ultrascale MPSoC FPGA Manager Device Tree Bindings

maintainers:

  - Nava kishore Manne <navam@xilinx.com>

description: |

  Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.

  The ZynqMP SoC uses the PCAP (Processor Configuration Port) to

  configure the Programmable Logic (PL). The configuration uses the

  firmware interface.

properties:

  compatible:

    const: xlnx,zynqmp-pcap-fpga

required:

  - compatible

additionalProperties: false

examples:

  - |

    firmware {

      zynqmp_firmware: zynqmp-firmware {

        zynqmp_pcap: pcap {

          compatible = "xlnx,zynqmp-pcap-fpga";

        };

      };

    };

...