Unverified Commit d4dcdc53 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'qcom-arm64-for-5.19' of... 

Merge tag 'qcom-arm64-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 DT updates for v5.19

This adds MDIO bus description on the IPQ6018 platform.

On MSM8916 the BAM-DMUX WWAN network device is added and the Huawei
Ascend G7 gains sound card definition and clarified installation
instructions.

MSM8992 and MSM8994 continues to be worked on, gaining multimedia clock
controller, on-chip memory, watchdog and various cleanup changes. The
Xiaomi Mi 4C gains CPU regulators and fixes to the framebuffer
definition, while Huawei Nexus 6P gains eMMC support.

On MSM8996 the modem and sensor remtoeprocs are added and enabled in the
Dragonboard 820c and the Xiaomi devices.

On MSM8998 a few newly added clocks related to the sensor subsystem bus
are marked as protected by default and the OnePlus devices gains NFC.

The SC7180 platform and devices thereon are further polished and
limozeen moves to using edp-panel for EDID-based detection, over
statically defined panels.

On SC7280 GPI DMA, WiFi remoteproc and network device, LPASS audio
clocks, resets for SDCC controllers and a new CRD revision are added. A
supply glitch on the PCIe power and a current leak for Bluetooth during
suspend are corrected. The Herobrine board gains eDP support and the IDP
gains backlight. USB is marked wakeup capable.

On SDM845 the IPA, WLED based backlight and second WiFi channel are
enabled for Xiaomi Pocophone F1, the firmware name is modified to not
conflict with other boards.  On RB3 the CAN bus controller is added and
the WiFi calibration variant is defined to allow adding the board's
calibration information into linux-firmware.

SM6350 gains I2C busses, UFS and WiFi support, and the numbering of
uart9 is corrected.

On SM7225 and the Fairphone 4 UFS, WiFi and haptics are enabled.

On SM8150 PCIe, Ethernet and uSD card support is added, and enabled for
the SA8155p ADP board. The PDC interrupt controller is also added and
described as wakup interrupt parent for TLMM.

Camera subsystem and control interface are defined for SM8250. On the
Sony Xperia 1 II the audio amplifiers are enabled.

On SM8350 GPI DMA engines are added and linked to the I2C and SPI
serial engines. Surface Duo 2 gains battery charger support.

On SM8450 the two PCIe controller/PHYs are enabled, GPI DMA and QUP
serial engine instances are added. Remoteproc instances are enabled on
SM8450 HDK.

Last, but not least, a number of DeviceTree validation errors across
various boards are corrected.

* tag 'qcom-arm64-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (150 commits)
  arm64: dts: qcom: Only include sc7180.dtsi in sc7180-trogdor.dtsi
  arm64: dts: qcom: sc7180-trogdor: Simplify spi0/spi6 labeling
  arm64: dts: qcom: sc7180-trogdor: Simplify trackpad enabling
  arm64: dts: qcom: sc7280: eDP for herobrine boards
  arm64: dts: qcom: sa8155p-adp: Disable multiple Tx and Rx queues for ethernet IP
  arm64: dts: qcom: sm8150: Fix iommu sid value for SDC2 controller
  arm64: dts: qcom: sm8350-duo2: enable battery charger
  arm64: dts: qcom: Enable pm8350c pwm for sc7280-idp2
  arm64: dts: qcom: pm8350c: Add pwm support
  arm64: dts: qcom: sc7280-qcard: Configure CTS pin to bias-bus-hold for bluetooth
  arm64: dts: qcom: sc7280-idp: Configure CTS pin to bias-bus-hold for bluetooth
  arm64: dts: qcom: sc7180: Remove ipa interconnect node
  arm64: dts: qcom: sc7280-idp: Enable GPI DMAs
  arm64: dts: qcom: sc7280: Add GENI I2C/SPI DMA channels
  arm64: dts: qcom: sc7280: Add GPI DMAengines
  arm64: dts: qcom: sm8450: Fix qmp phy node (use phy@ instead of lanes@)
  arm64: dts: qcom: db845c: Add support for MCP2517FD
  arm64: dts: qcom: qrb5165-rb5: Fix can-clock node name
  arm64: dts: qcom: sc7280: Add SAR sensors to herobrine crd
  arm64: dts: qcom: sm8250: camss: Add CCI definitions
  ...

Link: https://lore.kernel.org/r/20220509204451.325675-1-bjorn.andersson@linaro.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 4c946669 19794489

Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml

0 → 100644
+172 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280



maintainers:

  - Taniya Das <tdas@codeaurora.org>



description: |

  Qualcomm LPASS core and audio clock control module which supports the

  clocks and power domains on SC7280.



  See also:

  - dt-bindings/clock/qcom,lpasscorecc-sc7280.h

  - dt-bindings/clock/qcom,lpassaudiocc-sc7280.h



properties:

  clocks: true



  clock-names: true



  compatible:

    enum:

      - qcom,sc7280-lpassaoncc

      - qcom,sc7280-lpassaudiocc

      - qcom,sc7280-lpasscorecc

      - qcom,sc7280-lpasshm



  power-domains:

    maxItems: 1



  '#clock-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#power-domain-cells'



additionalProperties: false



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: qcom,sc7280-lpassaudiocc



    then:

      properties:

        clocks:

          items:

            - description: Board XO source

            - description: LPASS_AON_CC_MAIN_RCG_CLK_SRC



        clock-names:

          items:

            - const: bi_tcxo

            - const: lpass_aon_cc_main_rcg_clk_src

  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sc7280-lpassaoncc



    then:

      properties:

        clocks:

          items:

            - description: Board XO source

            - description: Board XO active only source

            - description: LPASS_AON_CC_MAIN_RCG_CLK_SRC



        clock-names:

          items:

            - const: bi_tcxo

            - const: bi_tcxo_ao

            - const: iface



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sc7280-lpasshm

              - qcom,sc7280-lpasscorecc



    then:

      properties:

        clocks:

          items:

            - description: Board XO source



        clock-names:

          items:

            - const: bi_tcxo



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/clock/qcom,gcc-sc7280.h>

    #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>

    #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>

    lpass_audiocc: clock-controller@3300000 {

      compatible = "qcom,sc7280-lpassaudiocc";

      reg = <0x3300000 0x30000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;

      clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";

      power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;

      #clock-cells = <1>;

      #power-domain-cells = <1>;

    };



  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/clock/qcom,gcc-sc7280.h>

    #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>

    #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>

    lpass_hm: clock-controller@3c00000 {

      compatible = "qcom,sc7280-lpasshm";

      reg = <0x3c00000 0x28>;

      clocks = <&rpmhcc RPMH_CXO_CLK>;

      clock-names = "bi_tcxo";

      #clock-cells = <1>;

      #power-domain-cells = <1>;

    };



  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/clock/qcom,gcc-sc7280.h>

    #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>

    #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>

    lpasscore: clock-controller@3900000 {

      compatible = "qcom,sc7280-lpasscorecc";

      reg = <0x3900000 0x50000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>;

      clock-names = "bi_tcxo";

      power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;

      #clock-cells = <1>;

      #power-domain-cells = <1>;

    };



  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/clock/qcom,gcc-sc7280.h>

    #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>

    #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>

    lpass_aon: clock-controller@3380000 {

      compatible = "qcom,sc7280-lpassaoncc";

      reg = <0x3380000 0x30000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,

               <&lpasscore LPASS_CORE_CC_CORE_CLK>;

      clock-names = "bi_tcxo", "bi_tcxo_ao","iface";

      #clock-cells = <1>;

      #power-domain-cells = <1>;

    };



...

arch/arm64/boot/dts/qcom/Makefile

+3 −2
Original line number Diff line number Diff line
@@ -83,11 +83,12 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb 
dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-pompom-r3-lte.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-r1.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-r1-lte.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-herobrine-r0.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-crd.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-herobrine-r1.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-villager-r0.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp2.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-crd.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-crd-r3.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-ganges-kirin.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-nile-discovery.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-nile-pioneer.dtb

arch/arm64/boot/dts/qcom/apq8096-db820c.dts

+6 −0
Original line number Diff line number Diff line
@@ -258,6 +258,12 @@ 
	vdd-gfx-supply = <&vdd_gfx>;

};



&mss_pil {

	status = "okay";

	pll-supply = <&vreg_l12a_1p8>;

	firmware-name = "qcom/apq8096/mba.mbn", "qcom/apq8096/modem.mbn";

};



&pm8994_resin {

	status = "okay";

	linux,code = <KEY_VOLUMEDOWN>;

arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ 
	cs-select = <0>;

	status = "okay";



	m25p80@0 {

	flash@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0>;

arch/arm64/boot/dts/qcom/ipq6018.dtsi

+22 −12
Original line number Diff line number Diff line
@@ -318,12 +318,12 @@ 
			#size-cells = <0>;

			reg = <0x0 0x078b6000 0x0 0x600>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency  = <400000>;

			dmas = <&blsp_dma 15>, <&blsp_dma 14>;

			dma-names = "rx", "tx";

			dmas = <&blsp_dma 14>, <&blsp_dma 15>;

			dma-names = "tx", "rx";

			status = "disabled";

		};
@@ -333,12 +333,12 @@ 
			#size-cells = <0>;

			reg = <0x0 0x078b7000 0x0 0x600>;

			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;

			clock-names = "iface", "core";

			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			clock-frequency  = <400000>;

			dmas = <&blsp_dma 17>, <&blsp_dma 16>;

			dma-names = "rx", "tx";

			dmas = <&blsp_dma 16>, <&blsp_dma 17>;

			dma-names = "tx", "rx";

			status = "disabled";

		};
@@ -630,6 +630,16 @@ 
			};

		};



		mdio: mdio@90000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";

			reg = <0x0 0x90000 0x0 0x64>;

			clocks = <&gcc GCC_MDIO_AHB_CLK>;

			clock-names = "gcc_mdio_ahb_clk";

			status = "disabled";

		};



		qusb_phy_1: qusb@59000 {

			compatible = "qcom,ipq6018-qusb2-phy";

			reg = <0x0 0x059000 0x0 0x180>;
@@ -683,7 +693,6 @@ 
			reg = <0x0 0x78000 0x0 0x1C4>;

			#address-cells = <2>;

			#size-cells = <2>;

			#clock-cells = <1>;

			ranges;



			clocks = <&gcc GCC_USB0_AUX_CLK>,
@@ -695,12 +704,13 @@ 
			reset-names = "phy","common";

			status = "disabled";



			usb0_ssphy: lane@78200 {

			usb0_ssphy: phy@78200 {

				reg = <0x0 0x00078200 0x0 0x130>, /* Tx */

				      <0x0 0x00078400 0x0 0x200>, /* Rx */

				      <0x0 0x00078800 0x0 0x1F8>, /* PCS */

				      <0x0 0x00078600 0x0 0x044>; /* PCS misc */

				#phy-cells = <0>;

				#clock-cells = <1>;

				clocks = <&gcc GCC_USB0_PIPE_CLK>;

				clock-names = "pipe0";

				clock-output-names = "gcc_usb0_pipe_clk_src";