Merge branch 'master' of... (d4a7dbfd) · Commits · EulixOS / Software / Kernel

arch/powerpc/platforms/512x/mpc512x_shared.c

+9 −13

Original line number	Original line	Diff line number	Diff line
	@@ -66,8 +66,8 @@ struct fsl_diu_shared_fb {
	bool in_use;		bool in_use;
	};		};

	unsigned int mpc512x_get_pixel_format(unsigned int bits_per_pixel,		u32 mpc512x_get_pixel_format(enum fsl_diu_monitor_port port,
	int monitor_port)		unsigned int bits_per_pixel)
	{		{
	switch (bits_per_pixel) {		switch (bits_per_pixel) {
	case 32:		case 32:
	@@ -80,11 +80,12 @@ unsigned int mpc512x_get_pixel_format(unsigned int bits_per_pixel,
	return 0x00000400;		return 0x00000400;
	}		}

	void mpc512x_set_gamma_table(int monitor_port, char *gamma_table_base)		void mpc512x_set_gamma_table(enum fsl_diu_monitor_port port,
			char *gamma_table_base)
	{		{
	}		}

	void mpc512x_set_monitor_port(int monitor_port)		void mpc512x_set_monitor_port(enum fsl_diu_monitor_port port)
	{		{
	}		}

	@@ -182,14 +183,10 @@ void mpc512x_set_pixel_clock(unsigned int pixclock)
	iounmap(ccm);		iounmap(ccm);
	}		}

	ssize_t mpc512x_show_monitor_port(int monitor_port, char *buf)		enum fsl_diu_monitor_port
			mpc512x_valid_monitor_port(enum fsl_diu_monitor_port port)
	{		{
	return sprintf(buf, "0 - 5121 LCD\n");		return FSL_DIU_PORT_DVI;
	}

	int mpc512x_set_sysfs_monitor_port(int val)
	{
	return 0;
	}		}

	static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb;		static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb;
	@@ -332,8 +329,7 @@ void __init mpc512x_setup_diu(void)
	diu_ops.set_gamma_table = mpc512x_set_gamma_table;		diu_ops.set_gamma_table = mpc512x_set_gamma_table;
	diu_ops.set_monitor_port = mpc512x_set_monitor_port;		diu_ops.set_monitor_port = mpc512x_set_monitor_port;
	diu_ops.set_pixel_clock = mpc512x_set_pixel_clock;		diu_ops.set_pixel_clock = mpc512x_set_pixel_clock;
	diu_ops.show_monitor_port = mpc512x_show_monitor_port;		diu_ops.valid_monitor_port = mpc512x_valid_monitor_port;
	diu_ops.set_sysfs_monitor_port = mpc512x_set_sysfs_monitor_port;
	diu_ops.release_bootmem = mpc512x_release_bootmem;		diu_ops.release_bootmem = mpc512x_release_bootmem;
	#endif		#endif
	}		}

arch/powerpc/platforms/85xx/p1022_ds.c

+22 −25

Original line number	Original line	Diff line number	Diff line
	@@ -93,8 +93,8 @@
	* The Area Descriptor is a 32-bit value that determine which bits in each		* The Area Descriptor is a 32-bit value that determine which bits in each
	* pixel are to be used for each color.		* pixel are to be used for each color.
	*/		*/
	static unsigned int p1022ds_get_pixel_format(unsigned int bits_per_pixel,		static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port,
	int monitor_port)		unsigned int bits_per_pixel)
	{		{
	switch (bits_per_pixel) {		switch (bits_per_pixel) {
	case 32:		case 32:
	@@ -118,7 +118,8 @@ static unsigned int p1022ds_get_pixel_format(unsigned int bits_per_pixel,
	* On some boards, the gamma table for some ports may need to be modified.		* On some boards, the gamma table for some ports may need to be modified.
	* This is not the case on the P1022DS, so we do nothing.		* This is not the case on the P1022DS, so we do nothing.
	*/		*/
	static void p1022ds_set_gamma_table(int monitor_port, char *gamma_table_base)		static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
			char *gamma_table_base)
	{		{
	}		}

	@@ -126,7 +127,7 @@ static void p1022ds_set_gamma_table(int monitor_port, char *gamma_table_base)
	* p1022ds_set_monitor_port: switch the output to a different monitor port		* p1022ds_set_monitor_port: switch the output to a different monitor port
	*		*
	*/		*/
	static void p1022ds_set_monitor_port(int monitor_port)		static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
	{		{
	struct device_node *pixis_node;		struct device_node *pixis_node;
	void __iomem *pixis;		void __iomem *pixis;
	@@ -145,19 +146,21 @@ static void p1022ds_set_monitor_port(int monitor_port)
	}		}
	brdcfg1 = pixis + 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */		brdcfg1 = pixis + 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */

	switch (monitor_port) {		switch (port) {
	case 0: /* DVI */		case FSL_DIU_PORT_DVI:
			printk(KERN_INFO "%s:%u\n", __func__, __LINE__);
	/* Enable the DVI port, disable the DFP and the backlight */		/* Enable the DVI port, disable the DFP and the backlight */
	clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN \| PX_BRDCFG1_BACKLIGHT,		clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN \| PX_BRDCFG1_BACKLIGHT,
	PX_BRDCFG1_DVIEN);		PX_BRDCFG1_DVIEN);
	break;		break;
	case 1: /* Single link LVDS */		case FSL_DIU_PORT_LVDS:
			printk(KERN_INFO "%s:%u\n", __func__, __LINE__);
	/* Enable the DFP port, disable the DVI and the backlight */		/* Enable the DFP port, disable the DVI and the backlight */
	clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN \| PX_BRDCFG1_BACKLIGHT,		clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN \| PX_BRDCFG1_BACKLIGHT,
	PX_BRDCFG1_DFPEN);		PX_BRDCFG1_DFPEN);
	break;		break;
	default:		default:
	pr_err("p1022ds: unsupported monitor port %i\n", monitor_port);		pr_err("p1022ds: unsupported monitor port %i\n", port);
	}		}

	iounmap(pixis);		iounmap(pixis);
	@@ -214,23 +217,18 @@ void p1022ds_set_pixel_clock(unsigned int pixclock)
	}		}

	/**		/**
	* p1022ds_show_monitor_port: show the current monitor		* p1022ds_valid_monitor_port: set the monitor port for sysfs
	*
	* This function returns a string indicating whether the current monitor is
	* set to DVI or LVDS.
	*/		*/
	ssize_t p1022ds_show_monitor_port(int monitor_port, char *buf)		enum fsl_diu_monitor_port
			p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
	{		{
	return sprintf(buf, "%c0 - DVI\n%c1 - Single link LVDS\n",		switch (port) {
	monitor_port == 0 ? '' : ' ', monitor_port == 1 ? '' : ' ');		case FSL_DIU_PORT_DVI:
			case FSL_DIU_PORT_LVDS:
			return port;
			default:
			return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
	}		}

	/**
	* p1022ds_set_sysfs_monitor_port: set the monitor port for sysfs
	*/
	int p1022ds_set_sysfs_monitor_port(int val)
	{
	return val < 2 ? val : 0;
	}		}

	#endif		#endif
	@@ -305,8 +303,7 @@ static void __init p1022_ds_setup_arch(void)
	diu_ops.set_gamma_table = p1022ds_set_gamma_table;		diu_ops.set_gamma_table = p1022ds_set_gamma_table;
	diu_ops.set_monitor_port = p1022ds_set_monitor_port;		diu_ops.set_monitor_port = p1022ds_set_monitor_port;
	diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;		diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
	diu_ops.show_monitor_port = p1022ds_show_monitor_port;		diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
	diu_ops.set_sysfs_monitor_port = p1022ds_set_sysfs_monitor_port;
	#endif		#endif

	#ifdef CONFIG_SMP		#ifdef CONFIG_SMP

arch/powerpc/platforms/86xx/mpc8610_hpcd.c

+25 −30

Original line number	Original line	Diff line number	Diff line
	@@ -152,10 +152,10 @@ machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
	(c2 << AD_COMP_2_SHIFT) \| (c1 << AD_COMP_1_SHIFT) \| \		(c2 << AD_COMP_2_SHIFT) \| (c1 << AD_COMP_1_SHIFT) \| \
	(c0 << AD_COMP_0_SHIFT) \| (size << AD_PIXEL_S_SHIFT))		(c0 << AD_COMP_0_SHIFT) \| (size << AD_PIXEL_S_SHIFT))

	unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,		u32 mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port,
	int monitor_port)		unsigned int bits_per_pixel)
	{		{
	static const unsigned long pixelformat[][3] = {		static const u32 pixelformat[][3] = {
	{		{
	MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),		MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),
	MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),		MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),
	@@ -170,7 +170,8 @@ unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
	unsigned int arch_monitor;		unsigned int arch_monitor;

	/* The DVI port is mis-wired on revision 1 of this board. */		/* The DVI port is mis-wired on revision 1 of this board. */
	arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;		arch_monitor =
			((*pixis_arch == 0x01) && (port == FSL_DIU_PORT_DVI)) ? 0 : 1;

	switch (bits_per_pixel) {		switch (bits_per_pixel) {
	case 32:		case 32:
	@@ -185,10 +186,11 @@ unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
	}		}
	}		}

	void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)		void mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port,
			char *gamma_table_base)
	{		{
	int i;		int i;
	if (monitor_port == 2) { /* dual link LVDS */		if (port == FSL_DIU_PORT_DLVDS) {
	for (i = 0; i < 256*3; i++)		for (i = 0; i < 256*3; i++)
	gamma_table_base[i] = (gamma_table_base[i] << 2) \|		gamma_table_base[i] = (gamma_table_base[i] << 2) \|
	((gamma_table_base[i] >> 6) & 0x03);		((gamma_table_base[i] >> 6) & 0x03);
	@@ -199,17 +201,21 @@ void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
	#define PX_BRDCFG0_DLINK (1 << 4)		#define PX_BRDCFG0_DLINK (1 << 4)
	#define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL \| PX_BRDCFG0_DLINK)		#define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL \| PX_BRDCFG0_DLINK)

	void mpc8610hpcd_set_monitor_port(int monitor_port)		void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port)
	{		{
	static const u8 bdcfg[] = {		switch (port) {
	PX_BRDCFG0_DVISEL \| PX_BRDCFG0_DLINK,		case FSL_DIU_PORT_DVI:
	PX_BRDCFG0_DLINK,
	0,
	};

	if (monitor_port < 3)
	clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,		clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
	bdcfg[monitor_port]);		PX_BRDCFG0_DVISEL \| PX_BRDCFG0_DLINK);
			break;
			case FSL_DIU_PORT_LVDS:
			clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
			PX_BRDCFG0_DLINK);
			break;
			case FSL_DIU_PORT_DLVDS:
			clrbits8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK);
			break;
			}
	}		}

	/**		/**
	@@ -262,20 +268,10 @@ void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
	iounmap(guts);		iounmap(guts);
	}		}

	ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)		enum fsl_diu_monitor_port
	{		mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)
	return snprintf(buf, PAGE_SIZE,
	"%c0 - DVI\n"
	"%c1 - Single link LVDS\n"
	"%c2 - Dual link LVDS\n",
	monitor_port == 0 ? '*' : ' ',
	monitor_port == 1 ? '*' : ' ',
	monitor_port == 2 ? '*' : ' ');
	}

	int mpc8610hpcd_set_sysfs_monitor_port(int val)
	{		{
	return val < 3 ? val : 0;		return port;
	}		}

	#endif		#endif
	@@ -307,8 +303,7 @@ static void __init mpc86xx_hpcd_setup_arch(void)
	diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;		diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
	diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;		diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
	diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;		diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
	diu_ops.show_monitor_port = mpc8610hpcd_show_monitor_port;		diu_ops.valid_monitor_port = mpc8610hpcd_valid_monitor_port;
	diu_ops.set_sysfs_monitor_port = mpc8610hpcd_set_sysfs_monitor_port;
	#endif		#endif

	pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");		pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");

arch/powerpc/sysdev/fsl_soc.h

+17 −8

Original line number	Original line	Diff line number	Diff line
	@@ -22,14 +22,23 @@ struct device_node;
	extern void fsl_rstcr_restart(char *cmd);		extern void fsl_rstcr_restart(char *cmd);

	#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)		#if defined(CONFIG_FB_FSL_DIU) \|\| defined(CONFIG_FB_FSL_DIU_MODULE)

			/* The different ports that the DIU can be connected to */
			enum fsl_diu_monitor_port {
			FSL_DIU_PORT_DVI, /* DVI */
			FSL_DIU_PORT_LVDS, /* Single-link LVDS */
			FSL_DIU_PORT_DLVDS /* Dual-link LVDS */
			};

	struct platform_diu_data_ops {		struct platform_diu_data_ops {
	unsigned int (*get_pixel_format) (unsigned int bits_per_pixel,		u32 (*get_pixel_format)(enum fsl_diu_monitor_port port,
	int monitor_port);		unsigned int bpp);
	void (set_gamma_table) (int monitor_port, char gamma_table_base);		void (*set_gamma_table)(enum fsl_diu_monitor_port port,
	void (*set_monitor_port) (int monitor_port);		char *gamma_table_base);
			void (*set_monitor_port)(enum fsl_diu_monitor_port port);
	void (*set_pixel_clock)(unsigned int pixclock);		void (*set_pixel_clock)(unsigned int pixclock);
	ssize_t (show_monitor_port) (int monitor_port, char buf);		enum fsl_diu_monitor_port (*valid_monitor_port)
	int (*set_sysfs_monitor_port) (int val);		(enum fsl_diu_monitor_port port);
	void (*release_bootmem)(void);		void (*release_bootmem)(void);
	};		};

drivers/video/Kconfig

+13 −3

Original line number	Original line	Diff line number	Diff line
	@@ -259,6 +259,15 @@ config FB_TILEBLITTING
	comment "Frame buffer hardware drivers"		comment "Frame buffer hardware drivers"
	depends on FB		depends on FB

			config FB_GRVGA
			tristate "Aeroflex Gaisler framebuffer support"
			depends on FB && SPARC
			select FB_CFB_FILLRECT
			select FB_CFB_COPYAREA
			select FB_CFB_IMAGEBLIT
			---help---
			This enables support for the SVGACTRL framebuffer in the GRLIB IP library from Aeroflex Gaisler.

	config FB_CIRRUS		config FB_CIRRUS
	tristate "Cirrus Logic support"		tristate "Cirrus Logic support"
	depends on FB && (ZORRO \|\| PCI)		depends on FB && (ZORRO \|\| PCI)
	@@ -1756,9 +1765,10 @@ config FB_AU1100
	config FB_AU1200		config FB_AU1200
	bool "Au1200 LCD Driver"		bool "Au1200 LCD Driver"
	depends on (FB = y) && MIPS && SOC_AU1200		depends on (FB = y) && MIPS && SOC_AU1200
	select FB_CFB_FILLRECT		select FB_SYS_FILLRECT
	select FB_CFB_COPYAREA		select FB_SYS_COPYAREA
	select FB_CFB_IMAGEBLIT		select FB_SYS_IMAGEBLIT
			select FB_SYS_FOPS
	help		help
	This is the framebuffer driver for the AMD Au1200 SOC. It can drive		This is the framebuffer driver for the AMD Au1200 SOC. It can drive
	various panels and CRTs by passing in kernel cmd line option		various panels and CRTs by passing in kernel cmd line option