Commit d484dc2b authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue 



Tony Nguyen says:

====================
1GbE Intel Wired LAN Driver Updates 2021-08-24

Vinicius Costa Gomes says:

This adds support for PCIe PTM (Precision Time Measurement) to the igc
driver. PCIe PTM allows the NIC and Host clocks to be compared more
precisely, improving the clock synchronization accuracy.

Patch 1/4 reverts a commit that made pci_enable_ptm() private to the
PCI subsystem, reverting makes it possible for it to be called from
the drivers.

Patch 2/4 adds the pcie_ptm_enabled() helper.

Patch 3/4 calls pci_enable_ptm() from the igc driver.

Patch 4/4 implements the PCIe PTM support. Exposing it via the
.getcrosststamp() API implies that the time measurements are made
synchronously with the ioctl(). The hardware was implemented so the
most convenient way to retrieve that information would be
asynchronously. So, to follow the expectations of the ioctl() we have
to use less convenient ways, triggering an PCIe PTM dialog every time
a ioctl() is received.

Some questions are raised (also pointed out in the commit message):

1. Using convert_art_ns_to_tsc() is too x86 specific, there should be
   a common way to create a 'system_counterval_t' from a timestamp.

2. convert_art_ns_to_tsc() says that it should only be used when
   X86_FEATURE_TSC_KNOWN_FREQ is true, but during tests it works even
   when it returns false. Should that check be done?
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 38cbd6e7 a90ec848

drivers/net/ethernet/intel/igc/igc.h

+1 −0
Original line number Diff line number Diff line
@@ -227,6 +227,7 @@ struct igc_adapter { 
	struct timecounter tc;

	struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */

	ktime_t ptp_reset_start; /* Reset time in clock mono */

	struct system_time_snapshot snapshot;



	char fw_version[32];

drivers/net/ethernet/intel/igc/igc_defines.h

+31 −0
Original line number Diff line number Diff line
@@ -523,6 +523,37 @@ 
#define IGC_RXCSUM_CRCOFL	0x00000800   /* CRC32 offload enable */

#define IGC_RXCSUM_PCSD		0x00002000   /* packet checksum disabled */



/* PCIe PTM Control */

#define IGC_PTM_CTRL_START_NOW	BIT(29) /* Start PTM Now */

#define IGC_PTM_CTRL_EN		BIT(30) /* Enable PTM */

#define IGC_PTM_CTRL_TRIG	BIT(31) /* PTM Cycle trigger */

#define IGC_PTM_CTRL_SHRT_CYC(usec)	(((usec) & 0x2f) << 2)

#define IGC_PTM_CTRL_PTM_TO(usec)	(((usec) & 0xff) << 8)



#define IGC_PTM_SHORT_CYC_DEFAULT	10  /* Default Short/interrupted cycle interval */

#define IGC_PTM_CYC_TIME_DEFAULT	5   /* Default PTM cycle time */

#define IGC_PTM_TIMEOUT_DEFAULT		255 /* Default timeout for PTM errors */



/* PCIe Digital Delay */

#define IGC_PCIE_DIG_DELAY_DEFAULT	0x01440000



/* PCIe PHY Delay */

#define IGC_PCIE_PHY_DELAY_DEFAULT	0x40900000



#define IGC_TIMADJ_ADJUST_METH		0x40000000



/* PCIe PTM Status */

#define IGC_PTM_STAT_VALID		BIT(0) /* PTM Status */

#define IGC_PTM_STAT_RET_ERR		BIT(1) /* Root port timeout */

#define IGC_PTM_STAT_BAD_PTM_RES	BIT(2) /* PTM Response msg instead of PTM Response Data */

#define IGC_PTM_STAT_T4M1_OVFL		BIT(3) /* T4 minus T1 overflow */

#define IGC_PTM_STAT_ADJUST_1ST		BIT(4) /* 1588 timer adjusted during 1st PTM cycle */

#define IGC_PTM_STAT_ADJUST_CYC		BIT(5) /* 1588 timer adjusted during non-1st PTM cycle */



/* PCIe PTM Cycle Control */

#define IGC_PTM_CYCLE_CTRL_CYC_TIME(msec)	((msec) & 0x3ff) /* PTM Cycle Time (msec) */

#define IGC_PTM_CYCLE_CTRL_AUTO_CYC_EN		BIT(31) /* PTM Cycle Control */



/* GPY211 - I225 defines */

#define GPY_MMD_MASK		0xFFFF0000

#define GPY_MMD_SHIFT		16

drivers/net/ethernet/intel/igc/igc_main.c

+6 −0
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ 
#include <net/pkt_sched.h>

#include <linux/bpf_trace.h>

#include <net/xdp_sock_drv.h>

#include <linux/pci.h>



#include <net/ipv6.h>



#include "igc.h"
@@ -6174,6 +6176,10 @@ static int igc_probe(struct pci_dev *pdev, 


	pci_enable_pcie_error_reporting(pdev);



	err = pci_enable_ptm(pdev, NULL);

	if (err < 0)

		dev_info(&pdev->dev, "PCIe PTM not supported by PCIe bus/controller\n");



	pci_set_master(pdev);



	err = -ENOMEM;

drivers/net/ethernet/intel/igc/igc_ptp.c

+179 −0
Original line number Diff line number Diff line
@@ -9,6 +9,8 @@ 
#include <linux/ptp_classify.h>

#include <linux/clocksource.h>

#include <linux/ktime.h>

#include <linux/delay.h>

#include <linux/iopoll.h>



#define INCVALUE_MASK		0x7fffffff

#define ISGN			0x80000000
@@ -16,6 +18,9 @@ 
#define IGC_SYSTIM_OVERFLOW_PERIOD	(HZ * 60 * 9)

#define IGC_PTP_TX_TIMEOUT		(HZ * 15)



#define IGC_PTM_STAT_SLEEP		2

#define IGC_PTM_STAT_TIMEOUT		100



/* SYSTIM read access for I225 */

void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts)

{
@@ -752,6 +757,147 @@ int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) 
		-EFAULT : 0;

}



/* The two conditions below must be met for cross timestamping via

 * PCIe PTM:

 *

 * 1. We have an way to convert the timestamps in the PTM messages

 *    to something related to the system clocks (right now, only

 *    X86 systems with support for the Always Running Timer allow that);

 *

 * 2. We have PTM enabled in the path from the device to the PCIe root port.

 */

static bool igc_is_crosststamp_supported(struct igc_adapter *adapter)

{

	return IS_ENABLED(CONFIG_X86_TSC) ? pcie_ptm_enabled(adapter->pdev) : false;

}



static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp)

{

#if IS_ENABLED(CONFIG_X86_TSC)

	return convert_art_ns_to_tsc(tstamp);

#else

	return (struct system_counterval_t) { };

#endif

}



static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat)

{

	struct net_device *netdev = adapter->netdev;



	switch (ptm_stat) {

	case IGC_PTM_STAT_RET_ERR:

		netdev_err(netdev, "PTM Error: Root port timeout\n");

		break;

	case IGC_PTM_STAT_BAD_PTM_RES:

		netdev_err(netdev, "PTM Error: Bad response, PTM Response Data expected\n");

		break;

	case IGC_PTM_STAT_T4M1_OVFL:

		netdev_err(netdev, "PTM Error: T4 minus T1 overflow\n");

		break;

	case IGC_PTM_STAT_ADJUST_1ST:

		netdev_err(netdev, "PTM Error: 1588 timer adjusted during first PTM cycle\n");

		break;

	case IGC_PTM_STAT_ADJUST_CYC:

		netdev_err(netdev, "PTM Error: 1588 timer adjusted during non-first PTM cycle\n");

		break;

	default:

		netdev_err(netdev, "PTM Error: Unknown error (%#x)\n", ptm_stat);

		break;

	}

}



static int igc_phc_get_syncdevicetime(ktime_t *device,

				      struct system_counterval_t *system,

				      void *ctx)

{

	u32 stat, t2_curr_h, t2_curr_l, ctrl;

	struct igc_adapter *adapter = ctx;

	struct igc_hw *hw = &adapter->hw;

	int err, count = 100;

	ktime_t t1, t2_curr;



	/* Get a snapshot of system clocks to use as historic value. */

	ktime_get_snapshot(&adapter->snapshot);



	do {

		/* Doing this in a loop because in the event of a

		 * badly timed (ha!) system clock adjustment, we may

		 * get PTM errors from the PCI root, but these errors

		 * are transitory. Repeating the process returns valid

		 * data eventually.

		 */



		/* To "manually" start the PTM cycle we need to clear and

		 * then set again the TRIG bit.

		 */

		ctrl = rd32(IGC_PTM_CTRL);

		ctrl &= ~IGC_PTM_CTRL_TRIG;

		wr32(IGC_PTM_CTRL, ctrl);

		ctrl |= IGC_PTM_CTRL_TRIG;

		wr32(IGC_PTM_CTRL, ctrl);



		/* The cycle only starts "for real" when software notifies

		 * that it has read the registers, this is done by setting

		 * VALID bit.

		 */

		wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);



		err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat,

					 stat, IGC_PTM_STAT_SLEEP,

					 IGC_PTM_STAT_TIMEOUT);

		if (err < 0) {

			netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n");

			return err;

		}



		if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID)

			break;



		if (stat & ~IGC_PTM_STAT_VALID) {

			/* An error occurred, log it. */

			igc_ptm_log_error(adapter, stat);

			/* The STAT register is write-1-to-clear (W1C),

			 * so write the previous error status to clear it.

			 */

			wr32(IGC_PTM_STAT, stat);

			continue;

		}

	} while (--count);



	if (!count) {

		netdev_err(adapter->netdev, "Exceeded number of tries for PTM cycle\n");

		return -ETIMEDOUT;

	}



	t1 = ktime_set(rd32(IGC_PTM_T1_TIM0_H), rd32(IGC_PTM_T1_TIM0_L));



	t2_curr_l = rd32(IGC_PTM_CURR_T2_L);

	t2_curr_h = rd32(IGC_PTM_CURR_T2_H);



	/* FIXME: When the register that tells the endianness of the

	 * PTM registers are implemented, check them here and add the

	 * appropriate conversion.

	 */

	t2_curr_h = swab32(t2_curr_h);



	t2_curr = ((s64)t2_curr_h << 32 | t2_curr_l);



	*device = t1;

	*system = igc_device_tstamp_to_system(t2_curr);



	return 0;

}



static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp,

				  struct system_device_crosststamp *cts)

{

	struct igc_adapter *adapter = container_of(ptp, struct igc_adapter,

						   ptp_caps);



	return get_device_system_crosststamp(igc_phc_get_syncdevicetime,

					     adapter, &adapter->snapshot, cts);

}



/**

 * igc_ptp_init - Initialize PTP functionality

 * @adapter: Board private structure
@@ -788,6 +934,11 @@ void igc_ptp_init(struct igc_adapter *adapter) 
		adapter->ptp_caps.n_per_out = IGC_N_PEROUT;

		adapter->ptp_caps.n_pins = IGC_N_SDP;

		adapter->ptp_caps.verify = igc_ptp_verify_pin;



		if (!igc_is_crosststamp_supported(adapter))

			break;



		adapter->ptp_caps.getcrosststamp = igc_ptp_getcrosststamp;

		break;

	default:

		adapter->ptp_clock = NULL;
@@ -878,7 +1029,9 @@ void igc_ptp_stop(struct igc_adapter *adapter) 
void igc_ptp_reset(struct igc_adapter *adapter)

{

	struct igc_hw *hw = &adapter->hw;

	u32 cycle_ctrl, ctrl;

	unsigned long flags;

	u32 timadj;



	/* reset the tstamp_config */

	igc_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
@@ -887,12 +1040,38 @@ void igc_ptp_reset(struct igc_adapter *adapter) 


	switch (adapter->hw.mac.type) {

	case igc_i225:

		timadj = rd32(IGC_TIMADJ);

		timadj |= IGC_TIMADJ_ADJUST_METH;

		wr32(IGC_TIMADJ, timadj);



		wr32(IGC_TSAUXC, 0x0);

		wr32(IGC_TSSDP, 0x0);

		wr32(IGC_TSIM,

		     IGC_TSICR_INTERRUPTS |

		     (adapter->pps_sys_wrap_on ? IGC_TSICR_SYS_WRAP : 0));

		wr32(IGC_IMS, IGC_IMS_TS);



		if (!igc_is_crosststamp_supported(adapter))

			break;



		wr32(IGC_PCIE_DIG_DELAY, IGC_PCIE_DIG_DELAY_DEFAULT);

		wr32(IGC_PCIE_PHY_DELAY, IGC_PCIE_PHY_DELAY_DEFAULT);



		cycle_ctrl = IGC_PTM_CYCLE_CTRL_CYC_TIME(IGC_PTM_CYC_TIME_DEFAULT);



		wr32(IGC_PTM_CYCLE_CTRL, cycle_ctrl);



		ctrl = IGC_PTM_CTRL_EN |

			IGC_PTM_CTRL_START_NOW |

			IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) |

			IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT) |

			IGC_PTM_CTRL_TRIG;



		wr32(IGC_PTM_CTRL, ctrl);



		/* Force the first cycle to run. */

		wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);



		break;

	default:

		/* No work to do. */

drivers/net/ethernet/intel/igc/igc_regs.h

+23 −0
Original line number Diff line number Diff line
@@ -245,6 +245,29 @@ 
#define IGC_TXSTMPL	0x0B618  /* Tx timestamp value Low - RO */

#define IGC_TXSTMPH	0x0B61C  /* Tx timestamp value High - RO */



#define IGC_TIMADJ	0x0B60C  /* Time Adjustment Offset Register */



/* PCIe Registers */

#define IGC_PTM_CTRL		0x12540  /* PTM Control */

#define IGC_PTM_STAT		0x12544  /* PTM Status */

#define IGC_PTM_CYCLE_CTRL	0x1254C  /* PTM Cycle Control */



/* PTM Time registers */

#define IGC_PTM_T1_TIM0_L	0x12558  /* T1 on Timer 0 Low */

#define IGC_PTM_T1_TIM0_H	0x1255C  /* T1 on Timer 0 High */



#define IGC_PTM_CURR_T2_L	0x1258C  /* Current T2 Low */

#define IGC_PTM_CURR_T2_H	0x12590  /* Current T2 High */

#define IGC_PTM_PREV_T2_L	0x12584  /* Previous T2 Low */

#define IGC_PTM_PREV_T2_H	0x12588  /* Previous T2 High */

#define IGC_PTM_PREV_T4M1	0x12578  /* T4 Minus T1 on previous PTM Cycle */

#define IGC_PTM_CURR_T4M1	0x1257C  /* T4 Minus T1 on this PTM Cycle */

#define IGC_PTM_PREV_T3M2	0x12580  /* T3 Minus T2 on previous PTM Cycle */

#define IGC_PTM_TDELAY		0x12594  /* PTM PCIe Link Delay */



#define IGC_PCIE_DIG_DELAY	0x12550  /* PCIe Digital Delay */

#define IGC_PCIE_PHY_DELAY	0x12554  /* PCIe PHY Delay */



/* Management registers */

#define IGC_MANC	0x05820  /* Management Control - RW */