Commit d47d29a6 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE/IS_SANDYBRIDGE 



ILK is the only platform that we consider "gen5" and SNB is the only
platform we consider "gen6."  Add an IS_SANDYBRIDGE() macro and then
replace numeric platform tests for these two generations with direct
platform tests with the following Coccinelle semantic patch:

        @@ expression dev_priv; @@
        - IS_GEN(dev_priv, 5)
        + IS_IRONLAKE(dev_priv)

        @@ expression dev_priv; @@
        - IS_GEN(dev_priv, 6)
        + IS_SANDYBRIDGE(dev_priv)

        @@ expression dev_priv; @@
        - IS_GEN_RANGE(dev_priv, 5, 6)
        + IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)

This will simplify our upcoming patches which eliminate INTEL_GEN()
usage in the display code.

v2:
 - Reverse ilk/snb order for IS_GEN_RANGE conversion.  (Ville)
 - Rebase + regenerate from semantic patch

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210320044245.3920043-2-matthew.d.roper@intel.com
parent 5706d028

drivers/gpu/drm/i915/display/g4x_dp.c

+2 −2
Original line number Diff line number Diff line
@@ -234,7 +234,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, 
	 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI

	 * 2. Program DP PLL enable

	 */

	if (IS_GEN(dev_priv, 5))

	if (IS_IRONLAKE(dev_priv))

		intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);



	intel_dp->DP |= DP_PLL_ENABLE;
@@ -1368,7 +1368,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, 
		dig_port->dp.set_signal_levels = vlv_set_signal_levels;

	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)

		dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;

	else if (IS_GEN(dev_priv, 6) && port == PORT_A)

	else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)

		dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;

	else

		dig_port->dp.set_signal_levels = g4x_set_signal_levels;

drivers/gpu/drm/i915/display/i9xx_plane.c

+2 −2
Original line number Diff line number Diff line
@@ -161,8 +161,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, 


	dspcntr = DISPLAY_PLANE_ENABLE;



	if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||

	    IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))

	if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||

	    IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))

		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;



	switch (fb->format->format) {

drivers/gpu/drm/i915/display/intel_cdclk.c

+2 −2
Original line number Diff line number Diff line
@@ -2916,9 +2916,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
		dev_priv->display.get_cdclk = hsw_get_cdclk;

	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))

		dev_priv->display.get_cdclk = vlv_get_cdclk;

	else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))

	else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))

		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;

	else if (IS_GEN(dev_priv, 5))

	else if (IS_IRONLAKE(dev_priv))

		dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;

	else if (IS_GM45(dev_priv))

		dev_priv->display.get_cdclk = gm45_get_cdclk;

drivers/gpu/drm/i915/display/intel_cursor.c

+1 −1
Original line number Diff line number Diff line
@@ -360,7 +360,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, 
		to_i915(plane_state->uapi.plane->dev);

	u32 cntl = 0;



	if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))

	if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))

		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;



	switch (drm_rect_width(&plane_state->uapi.dst)) {

drivers/gpu/drm/i915/display/intel_display.c

+6 −6
Original line number Diff line number Diff line
@@ -361,7 +361,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, 
	u32 val;



	/* ILK FDI PLL is always enabled */

	if (IS_GEN(dev_priv, 5))

	if (IS_IRONLAKE(dev_priv))

		return;



	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
@@ -7441,7 +7441,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat 
	 * plane, not only sprite plane.

	 */

	if (plane->id != PLANE_CURSOR &&

	    (IS_GEN_RANGE(dev_priv, 5, 6) ||

	    (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||

	     IS_IVYBRIDGE(dev_priv)) &&

	    (turn_on || (!needs_scaling(old_plane_state) &&

			 needs_scaling(plane_state))))
@@ -11606,7 +11606,7 @@ static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) 
	if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)

		return false;



	if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))

	if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))

		return false;



	return true;
@@ -12418,12 +12418,12 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv) 


static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)

{

	if (IS_GEN(dev_priv, 5)) {

	if (IS_IRONLAKE(dev_priv)) {

		u32 fdi_pll_clk =

			intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;



		dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;

	} else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {

	} else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {

		dev_priv->fdi_pll_freq = 270000;

	} else {

		return;
@@ -13068,7 +13068,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) 
	 * without several WARNs, but for now let's take the easy

	 * road.

	 */

	return IS_GEN(dev_priv, 6) &&

	return IS_SANDYBRIDGE(dev_priv) &&

		crtc_state->hw.active &&

		crtc_state->shared_dpll &&

		crtc_state->port_clock == 0;