Commit d46e5245 authored by Marc Zyngier's avatar Marc Zyngier Committed by chenxiang
Browse files

KVM: arm64: vgic-v3: Upgrade AP1Rn to 64bit. 

virt inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I97WGU

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/commit/?h=arm64/nmi&id=613fbb4e6f00351cdf2f7462bbc479f239383055



----------------------------------------------------------------

With the advent of FEAT_GIC_NMI, ICH_AP1R0_EL2 is now a 64bit
register, as the NMI priority is encoded in bit 63.

Upgrade the whole of the AP1Rn array to 64bit, leaving the
Group0 equivalent to 32bit.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarXiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: default avatarcaijian <caijian11@h-partners.com>
parent 05607873

arch/arm64/kvm/hyp/vgic-v3-sr.c

+8 −3
Original line number Diff line number Diff line
@@ -130,7 +130,11 @@ static void __vgic_v3_write_ap0rn(u32 val, int n) 
	}

}



static void __vgic_v3_write_ap1rn(u32 val, int n)

/*

 * Contrary to ICH_AP0Rn_EL2, ICH_AP1R0_EL2 is 64bit, thanks to the

 * NMI bit stuck at [63]. Isn't that fun?

 */

static void __vgic_v3_write_ap1rn(u64 val, int n)

{

	switch (n) {

	case 0:
@@ -172,9 +176,10 @@ static u32 __vgic_v3_read_ap0rn(int n) 
	return val;

}



static u32 __vgic_v3_read_ap1rn(int n)

/* Same remark about the 64bit-ness of AP1R0 */

static u64 __vgic_v3_read_ap1rn(int n)

{

	u32 val;

	u64 val;



	switch (n) {

	case 0:

include/kvm/arm_vgic.h

+1 −1
Original line number Diff line number Diff line
@@ -375,7 +375,7 @@ struct vgic_v3_cpu_if { 
	u32		vgic_vmcr;

	u32		vgic_sre;	/* Restored only, change ignored */

	u32		vgic_ap0r[4];

	u32		vgic_ap1r[4];

	u64		vgic_ap1r[4];

	u64		vgic_lr[VGIC_V3_MAX_LRS];



	/*