Commit d46549c6 authored by WenChun Fei's avatar WenChun Fei Committed by Weibo Zhao
Browse files

hns3 udma: add prefix hns3 for udma. 

driver inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IAE3IT


CVE: NA

--------------------------------------------------------

the patch added prefix hns3 for udma in struct, macro
and func of udma driver.

Fixes: 9c9b2869 ("hns3 udma: cmd and mailbox for hns3-udma driver ")
Signed-off-by: default avatarWenChun Fei <feiwenchun@huawei.com>
Signed-off-by: default avatarWeibo Zhao <zhaoweibo3@huawei.com>
parent d33f3d85

drivers/ub/hw/hns3/hns3_udma_abi.h

+27 −27
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Huawei UDMA Linux driver

/* Huawei HNS3_UDMA Linux driver

 * Copyright (c) 2023-2023 Hisilicon Limited.

 *

 * This program is free software; you can redistribute it and/or modify it
@@ -162,10 +162,10 @@ struct hns3_udma_create_ctx_ucmd { 
};



enum hns3_udma_context_comp_mask {

	UDMA_CONTEXT_MASK_DCA_PRIME_QPS = 1 << 0,

	UDMA_CONTEXT_MASK_DCA_UNIT_SIZE = 1 << 1,

	UDMA_CONTEXT_MASK_DCA_MAX_SIZE = 1 << 2,

	UDMA_CONTEXT_MASK_DCA_MIN_SIZE = 1 << 3,

	HNS3_UDMA_CONTEXT_MASK_DCA_PRIME_QPS = 1 << 0,

	HNS3_UDMA_CONTEXT_MASK_DCA_UNIT_SIZE = 1 << 1,

	HNS3_UDMA_CONTEXT_MASK_DCA_MAX_SIZE = 1 << 2,

	HNS3_UDMA_CONTEXT_MASK_DCA_MIN_SIZE = 1 << 3,

};



struct hns3_udma_create_ctx_resp {
@@ -195,72 +195,72 @@ struct flush_cqe_param { 
	uint32_t sq_producer_idx;

};



struct udma_poe_info {

struct hns3_udma_poe_info {

	uint8_t		en;

	uint8_t		poe_channel;

	uint64_t	poe_addr;

};



struct udma_dca_reg_attr {

struct hns3_udma_dca_reg_attr {

	uintptr_t	key;

	uintptr_t	addr;

	uint32_t	size;

};



struct udma_dca_dereg_attr {

struct hns3_udma_dca_dereg_attr {

	uintptr_t	free_key;

	struct dca_mem	*mem;

};



struct udma_dca_shrink_attr {

struct hns3_udma_dca_shrink_attr {

	uint64_t reserved_size;

};



struct udma_dca_shrink_resp {

struct hns3_udma_dca_shrink_resp {

	struct dca_mem	*mem;

	uintptr_t	free_key;

	uint32_t	free_mems;

};



struct udma_dca_attach_attr {

struct hns3_udma_dca_attach_attr {

	uint64_t	qpn;

	uint32_t	sq_offset;

	uint32_t	sge_offset;

};



struct udma_dca_attach_resp {

struct hns3_udma_dca_attach_resp {

	uint32_t	alloc_flags;

	uint32_t	alloc_pages;

	uint32_t	dcan;

};



struct udma_dca_detach_attr {

struct hns3_udma_dca_detach_attr {

	uint64_t	qpn;

	uint32_t	sq_idx;

};



struct udma_dca_query_attr {

struct hns3_udma_dca_query_attr {

	uint64_t	qpn;

	uint32_t	page_idx;

};



struct udma_dca_query_resp {

struct hns3_udma_dca_query_resp {

	uintptr_t	mem_key;

	uint32_t	mem_ofs;

	uint32_t	page_count;

};



enum hns3_udma_user_ctl_handlers {

	UDMA_USER_CTL_FLUSH_CQE,

	UDMA_CONFIG_POE_CHANNEL,

	UDMA_QUERY_POE_CHANNEL,

	UDMA_DCA_MEM_REG,

	UDMA_DCA_MEM_DEREG,

	UDMA_DCA_MEM_SHRINK,

	UDMA_DCA_MEM_ATTACH,

	UDMA_DCA_MEM_DETACH,

	UDMA_DCA_MEM_QUERY,

	UDMA_OPCODE_NUM,

	HNS3_UDMA_USER_CTL_FLUSH_CQE,

	HNS3_UDMA_CONFIG_POE_CHANNEL,

	HNS3_UDMA_QUERY_POE_CHANNEL,

	HNS3_UDMA_DCA_MEM_REG,

	HNS3_UDMA_DCA_MEM_DEREG,

	HNS3_UDMA_DCA_MEM_SHRINK,

	HNS3_UDMA_DCA_MEM_ATTACH,

	HNS3_UDMA_DCA_MEM_DETACH,

	HNS3_UDMA_DCA_MEM_QUERY,

	HNS3_UDMA_OPCODE_NUM,

};



#endif /* _HNS3_UDMA_ABI_H */

drivers/ub/hw/hns3/hns3_udma_cmd.c

+134 −127
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/* Huawei UDMA Linux driver

/* Huawei HNS3_UDMA Linux driver

 * Copyright (c) 2023-2023 Hisilicon Limited.

 *

 * This program is free software; you can redistribute it and/or modify it
@@ -23,14 +23,15 @@ 
static int debug_switch = 1;

static int cnt_mailbox = 1;



int udma_cmd_init(struct udma_dev *udma_dev)

int hns3_udma_cmd_init(struct hns3_udma_dev *udma_dev)

{

	sema_init(&udma_dev->cmd.poll_sem, 1);

	udma_dev->cmd.use_events = 0;

	udma_dev->cmd.max_cmds = CMD_MAX_NUM;

	udma_dev->cmd.pool = dma_pool_create("udma_cmd", udma_dev->dev,

					     UDMA_MAILBOX_SIZE,

					     UDMA_MAILBOX_SIZE, 0);

	udma_dev->cmd.pool = dma_pool_create("hns3_udma_cmd",

					     udma_dev->dev,

					     HNS3_UDMA_MAILBOX_SIZE,

					     HNS3_UDMA_MAILBOX_SIZE, 0);

	if (!udma_dev->cmd.pool)

		return -ENOMEM;
@@ -39,19 +40,20 @@ int udma_cmd_init(struct udma_dev *udma_dev) 
	return 0;

}



void udma_cmd_cleanup(struct udma_dev *udma_dev)

void hns3_udma_cmd_cleanup(struct hns3_udma_dev *udma_dev)

{

	down_write(&udma_dev->cmd.udma_mb_rwsem);

	dma_pool_destroy(udma_dev->cmd.pool);

	up_write(&udma_dev->cmd.udma_mb_rwsem);

}



int udma_cmd_use_events(struct udma_dev *udma_dev)

int hns3_udma_cmd_use_events(struct hns3_udma_dev *udma_dev)

{

	struct udma_cmdq *udma_cmd = &udma_dev->cmd;

	struct hns3_udma_cmdq *udma_cmd = &udma_dev->cmd;

	int i;



	udma_cmd->context = kcalloc(udma_cmd->max_cmds, sizeof(*udma_cmd->context),

	udma_cmd->context = kcalloc(udma_cmd->max_cmds,

				    sizeof(*udma_cmd->context),

				    GFP_KERNEL);

	if (!udma_cmd->context)

		return -ENOMEM;
@@ -72,17 +74,17 @@ int udma_cmd_use_events(struct udma_dev *udma_dev) 
	return 0;

}



void udma_cmd_use_polling(struct udma_dev *udma_dev)

void hns3_udma_cmd_use_polling(struct hns3_udma_dev *udma_dev)

{

	struct udma_cmdq *udma_cmd = &udma_dev->cmd;

	struct hns3_udma_cmdq *udma_cmd = &udma_dev->cmd;



	kfree(udma_cmd->context);

	udma_cmd->use_events = 0;

}



struct udma_cmd_mailbox *udma_alloc_cmd_mailbox(struct udma_dev *dev)

struct hns3_udma_cmd_mailbox *hns3_udma_alloc_cmd_mailbox(struct hns3_udma_dev *dev)

{

	struct udma_cmd_mailbox *mailbox;

	struct hns3_udma_cmd_mailbox *mailbox;



	mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);

	if (!mailbox)
@@ -101,8 +103,8 @@ struct udma_cmd_mailbox *udma_alloc_cmd_mailbox(struct udma_dev *dev) 
	return mailbox;

}



void udma_free_cmd_mailbox(struct udma_dev *dev,

			   struct udma_cmd_mailbox *mailbox)

void hns3_udma_free_cmd_mailbox(struct hns3_udma_dev *dev,

				struct hns3_udma_cmd_mailbox *mailbox)

{

	if (!mailbox)

		return;
@@ -114,7 +116,7 @@ void udma_free_cmd_mailbox(struct udma_dev *dev, 
	kfree(mailbox);

}



static uint32_t udma_cmd_hw_reseted(struct udma_dev *dev,

static uint32_t hns3_udma_cmd_hw_reseted(struct hns3_udma_dev *dev,

					 uint64_t instance_stage,

					 uint64_t reset_stage)

{
@@ -130,20 +132,20 @@ static uint32_t udma_cmd_hw_reseted(struct udma_dev *dev, 
	dev->is_reset = true;

	dev->dis_db = true;



	if (reset_stage == UDMA_STATE_RST_INIT ||

	    instance_stage == UDMA_STATE_INIT)

	if (reset_stage == HNS3_UDMA_STATE_RST_INIT ||

	    instance_stage == HNS3_UDMA_STATE_INIT)

		return CMD_RST_PRC_EBUSY;



	return CMD_RST_PRC_SUCCESS;

}



static uint32_t udma_cmd_hw_resetting(struct udma_dev *dev,

static uint32_t hns3_udma_cmd_hw_resetting(struct hns3_udma_dev *dev,

					   uint64_t instance_stage,

					   uint64_t reset_stage)

{

#define HW_RESET_TIMEOUT_US 1000000

#define HW_RESET_DELAY_US 1

	struct udma_priv *priv = (struct udma_priv *)dev->priv;

	struct hns3_udma_priv *priv = (struct hns3_udma_priv *)dev->priv;

	struct hnae3_handle *handle = priv->handle;

	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;

	uint64_t val;
@@ -167,16 +169,16 @@ static uint32_t udma_cmd_hw_resetting(struct udma_dev *dev, 
	if (!ret)

		dev->is_reset = true;



	if (!dev->is_reset || reset_stage == UDMA_STATE_RST_INIT ||

	    instance_stage == UDMA_STATE_INIT)

	if (!dev->is_reset || reset_stage == HNS3_UDMA_STATE_RST_INIT ||

	    instance_stage == HNS3_UDMA_STATE_INIT)

		return CMD_RST_PRC_EBUSY;



	return CMD_RST_PRC_SUCCESS;

}



static uint32_t udma_cmd_sw_resetting(struct udma_dev *dev)

static uint32_t hns3_udma_cmd_sw_resetting(struct hns3_udma_dev *dev)

{

	struct udma_priv *priv = (struct udma_priv *)dev->priv;

	struct hns3_udma_priv *priv = (struct hns3_udma_priv *)dev->priv;

	struct hnae3_handle *handle = priv->handle;

	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
@@ -191,7 +193,7 @@ static uint32_t udma_cmd_sw_resetting(struct udma_dev *dev) 
	return CMD_RST_PRC_EBUSY;

}



static uint32_t check_aedev_reset_status(struct udma_dev *dev,

static uint32_t check_aedev_reset_status(struct hns3_udma_dev *dev,

					 struct hnae3_handle *handle)

{

	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
@@ -211,22 +213,22 @@ static uint32_t check_aedev_reset_status(struct udma_dev *dev, 
	reset_stage = handle->udmainfo.reset_state;

	reset_cnt = ops->ae_dev_reset_cnt(handle);

	if (reset_cnt != dev->reset_cnt)

		return udma_cmd_hw_reseted(dev, instance_stage, reset_stage);

		return hns3_udma_cmd_hw_reseted(dev, instance_stage, reset_stage);



	hw_resetting = ops->get_cmdq_stat(handle);

	if (hw_resetting)

		return udma_cmd_hw_resetting(dev, instance_stage, reset_stage);

		return hns3_udma_cmd_hw_resetting(dev, instance_stage, reset_stage);



	sw_resetting = ops->ae_dev_resetting(handle);

	if (sw_resetting && instance_stage == UDMA_STATE_INIT)

		return udma_cmd_sw_resetting(dev);

	if (sw_resetting && instance_stage == HNS3_UDMA_STATE_INIT)

		return hns3_udma_cmd_sw_resetting(dev);



	return CMD_RST_PRC_OTHERS;

}



bool udma_chk_mbox_is_avail(struct udma_dev *dev, bool *busy)

bool hns3_udma_chk_mbox_is_avail(struct hns3_udma_dev *dev, bool *busy)

{

	struct udma_priv *priv = (struct udma_priv *)dev->priv;

	struct hns3_udma_priv *priv = (struct hns3_udma_priv *)dev->priv;

	uint32_t status;



	/*
@@ -234,7 +236,7 @@ bool udma_chk_mbox_is_avail(struct udma_dev *dev, bool *busy) 
	 * unresponsive state, CMDQ command needs to return quickly,

	 * in order to avoid excessive printing, return CMD_RST_PRC_SUCCESS.

	 */

	if (dev->cmd.state == UDMA_CMDQ_STATE_FATAL_ERR ||

	if (dev->cmd.state == HNS3_UDMA_CMDQ_STATE_FATAL_ERR ||

	    dev->is_reset)

		status = CMD_RST_PRC_SUCCESS;

	else
@@ -245,62 +247,68 @@ bool udma_chk_mbox_is_avail(struct udma_dev *dev, bool *busy) 
	return status == CMD_RST_PRC_OTHERS;

}



static int udma_cmq_csq_done(struct udma_dev *dev)

static int hns3_udma_cmq_csq_done(struct hns3_udma_dev *dev)

{

	struct udma_priv *priv = (struct udma_priv *)dev->priv;

	uint32_t tail = ub_read(dev, UDMA_TX_CMQ_CI_REG);

	struct hns3_udma_priv *priv = (struct hns3_udma_priv *)dev->priv;

	uint32_t tail = ub_read(dev, HNS3_UDMA_TX_CMQ_CI_REG);



	return tail == priv->cmq.csq.head;

}



void udma_cmq_setup_basic_desc(struct udma_cmq_desc *desc,

			       enum udma_opcode_type opcode,

void hns3_udma_cmq_setup_basic_desc(struct hns3_udma_cmq_desc *desc,

				    enum hns3_udma_opcode_type opcode,

				    bool is_read)

{

	memset((void *)desc, 0, sizeof(struct udma_cmq_desc));

	memset((void *)desc, 0, sizeof(struct hns3_udma_cmq_desc));

	desc->opcode = cpu_to_le16(opcode);

	desc->flag =

		cpu_to_le16(UDMA_CMD_FLAG_NO_INTR | UDMA_CMD_FLAG_IN);

		cpu_to_le16(HNS3_UDMA_CMD_FLAG_NO_INTR | HNS3_UDMA_CMD_FLAG_IN);

	if (is_read)

		desc->flag |= cpu_to_le16(UDMA_CMD_FLAG_WR);

		desc->flag |= cpu_to_le16(HNS3_UDMA_CMD_FLAG_WR);

	else

		desc->flag &= cpu_to_le16(~UDMA_CMD_FLAG_WR);

		desc->flag &= cpu_to_le16(~HNS3_UDMA_CMD_FLAG_WR);

}



static void dump_desc(struct udma_dev *dev,

		      struct udma_cmq_desc *desc)

static void dump_desc(struct hns3_udma_dev *dev,

		      struct hns3_udma_cmq_desc *desc)

{

	static int num_mailbox;

	static uint32_t num_mailbox;



	if (desc->opcode == UDMA_OPC_QUERY_MB_ST ||

	    desc->opcode == UDMA_OPC_CFG_GMV_BT)

	if (desc->opcode == HNS3_UDMA_OPC_QUERY_MB_ST ||

	    desc->opcode == HNS3_UDMA_OPC_CFG_GMV_BT)

		return;



	if (desc->opcode == UDMA_OPC_POST_MB && cnt_mailbox)

	if (desc->opcode == HNS3_UDMA_OPC_POST_MB && cnt_mailbox)

		++num_mailbox;



	if (((desc->data[SUB_OPCODE_IDX] & 0xFF) ==

	     UDMA_CMD_WRITE_QPC_TIMER_BT0) ||

	     HNS3_UDMA_CMD_WRITE_QPC_TIMER_BT0) ||

	    ((desc->data[SUB_OPCODE_IDX] & 0xFF) ==

	     UDMA_CMD_WRITE_CQC_TIMER_BT0))

	     HNS3_UDMA_CMD_WRITE_CQC_TIMER_BT0))

		dev_err_ratelimited(dev->dev,

			"send cmd opcode:0x%4x, data: %08x %08x %08x %08x %08x %08x, mlbox: %08x\n",

			desc->opcode, desc->data[0], desc->data[1],

			desc->data[2], desc->data[3], desc->data[4],

			desc->data[5], num_mailbox);

		"send cmd opcode:0x%4x, data: %08x %08x %08x %08x %08x %08x, mlbox: 0x%08x\n",

		desc->opcode, desc->data[HNS3_UDMA_CMQ_DESC_DATA_0],

		desc->data[HNS3_UDMA_CMQ_DESC_DATA_1],

		desc->data[HNS3_UDMA_CMQ_DESC_DATA_2],

		desc->data[HNS3_UDMA_CMQ_DESC_DATA_3],

		desc->data[HNS3_UDMA_CMQ_DESC_DATA_4],

		desc->data[HNS3_UDMA_CMQ_DESC_DATA_5], num_mailbox);

	else

		dev_info_ratelimited(dev->dev,

			"send cmd opcode:0x%4x, data: %08x %08x %08x %08x %08x %08x, mlbox: %08x\n",

			desc->opcode, desc->data[0], desc->data[1],

			desc->data[2], desc->data[3], desc->data[4],

			desc->data[5], num_mailbox);

		"send cmd opcode:0x%4x, data: %08x %08x %08x %08x %08x %08x, mlbox: 0x%08x\n",

		desc->opcode, desc->data[HNS3_UDMA_CMQ_DESC_DATA_0],

		desc->data[HNS3_UDMA_CMQ_DESC_DATA_1],

		desc->data[HNS3_UDMA_CMQ_DESC_DATA_2],

		desc->data[HNS3_UDMA_CMQ_DESC_DATA_3],

		desc->data[HNS3_UDMA_CMQ_DESC_DATA_4],

		desc->data[HNS3_UDMA_CMQ_DESC_DATA_5], num_mailbox);

}



static int __udma_cmq_send(struct udma_dev *dev, struct udma_cmq_desc *desc,

static int __hns3_udma_cmq_send(struct hns3_udma_dev *dev, struct hns3_udma_cmq_desc *desc,

				int num)

{

	struct udma_priv *priv = (struct udma_priv *)dev->priv;

	struct udma_cmq_ring *csq = &priv->cmq.csq;

	struct hns3_udma_priv *priv = (struct hns3_udma_priv *)dev->priv;

	struct hns3_udma_cmq_ring *csq = &priv->cmq.csq;

	uint32_t timeout = 0;

	uint16_t desc_ret;

	uint32_t tail;
@@ -325,15 +333,15 @@ static int __udma_cmq_send(struct udma_dev *dev, struct udma_cmq_desc *desc, 
	wmb();



	/* Write to hardware */

	ub_write(dev, UDMA_TX_CMQ_PI_REG, csq->head);

	ub_write(dev, HNS3_UDMA_TX_CMQ_PI_REG, csq->head);



	do {

		if (udma_cmq_csq_done(dev))

		if (hns3_udma_cmq_csq_done(dev))

			break;

		udelay(1);

	} while (++timeout < priv->cmq.tx_timeout);



	if (udma_cmq_csq_done(dev)) {

	if (hns3_udma_cmq_csq_done(dev)) {

		for (i = 0; i < num; i++) {

			/* check the result of hardware write back */

			desc[i] = csq->desc[tail++];
@@ -351,12 +359,12 @@ static int __udma_cmq_send(struct udma_dev *dev, struct udma_cmq_desc *desc, 
		}

	} else {

		/* FW/HW reset or incorrect number of desc */

		tail = ub_read(dev, UDMA_TX_CMQ_CI_REG);

		tail = ub_read(dev, HNS3_UDMA_TX_CMQ_CI_REG);

		dev_warn(dev->dev, "CMDQ move tail from %u to %u.\n",

			 csq->head, tail);

		csq->head = tail;



		dev->cmd.state = UDMA_CMDQ_STATE_HEAD_TAIL_ERR;

		dev->cmd.state = HNS3_UDMA_CMDQ_STATE_HEAD_TAIL_ERR;



		ret = -EAGAIN;

	}
@@ -366,46 +374,46 @@ static int __udma_cmq_send(struct udma_dev *dev, struct udma_cmq_desc *desc, 
	return ret;

}



int udma_cmq_send(struct udma_dev *dev, struct udma_cmq_desc *desc, int num)

int hns3_udma_cmq_send(struct hns3_udma_dev *dev, struct hns3_udma_cmq_desc *desc, int num)

{

	bool busy;

	int ret;



	if (!udma_chk_mbox_is_avail(dev, &busy))

	if (!hns3_udma_chk_mbox_is_avail(dev, &busy))

		return busy ? -EBUSY : 0;



	ret = __udma_cmq_send(dev, desc, num);

	ret = __hns3_udma_cmq_send(dev, desc, num);

	if (ret) {

		if (!udma_chk_mbox_is_avail(dev, &busy))

		if (!hns3_udma_chk_mbox_is_avail(dev, &busy))

			return busy ? -EBUSY : 0;

	}



	return ret;

}



static int udma_wait_mbox_complete(struct udma_dev *dev, uint32_t timeout,

static int hns3_udma_wait_mbox_complete(struct hns3_udma_dev *dev, uint32_t timeout,

					uint8_t *complete_status)

{

	struct udma_mbox_status *mb_st;

	struct udma_cmq_desc desc;

	struct hns3_udma_mbox_status *mb_st;

	struct hns3_udma_cmq_desc desc;

	unsigned long end;

	int ret = -EBUSY;

	uint32_t status;

	bool busy;



	mb_st = (struct udma_mbox_status *)desc.data;

	mb_st = (struct hns3_udma_mbox_status *)desc.data;

	end = msecs_to_jiffies(timeout) + jiffies;

	while (udma_chk_mbox_is_avail(dev, &busy)) {

	while (hns3_udma_chk_mbox_is_avail(dev, &busy)) {

		status = 0;

		udma_cmq_setup_basic_desc(&desc, UDMA_OPC_QUERY_MB_ST,

		hns3_udma_cmq_setup_basic_desc(&desc, HNS3_UDMA_OPC_QUERY_MB_ST,

					       true);

		ret = __udma_cmq_send(dev, &desc, 1);

		ret = __hns3_udma_cmq_send(dev, &desc, 1);

		if (!ret) {

			status = le32_to_cpu(mb_st->mb_status_hw_run);

			/* No pending message exists in UDMA mbox. */

			/* No pending message exists in HNS3_UDMA mbox. */

			if (!(status & MB_ST_HW_RUN_M))

				break;

		} else if (!udma_chk_mbox_is_avail(dev, &busy)) {

		} else if (!hns3_udma_chk_mbox_is_avail(dev, &busy)) {

			break;

		}
@@ -422,7 +430,7 @@ static int udma_wait_mbox_complete(struct udma_dev *dev, uint32_t timeout, 


	if (!ret) {

		*complete_status = (uint8_t)(status & MB_ST_COMPLETE_M);

	} else if (!udma_chk_mbox_is_avail(dev, &busy)) {

	} else if (!hns3_udma_chk_mbox_is_avail(dev, &busy)) {

		/* Ignore all errors if the mbox is unavailable. */

		ret = busy ? -EBUSY : 0;

		*complete_status = MB_ST_COMPLETE_M;
@@ -431,25 +439,24 @@ static int udma_wait_mbox_complete(struct udma_dev *dev, uint32_t timeout, 
	return ret;

}



static int __udma_post_mbox(struct udma_dev *dev, struct udma_cmq_desc *desc,

static int __hns3_udma_post_mbox(struct hns3_udma_dev *dev, struct hns3_udma_cmq_desc *desc,

				 uint16_t token, int vfid_event)

{

	struct udma_mbox *mb = (struct udma_mbox *)desc->data;

	struct hns3_udma_mbox *mb = (struct hns3_udma_mbox *)desc->data;



	mb->token_event_en = cpu_to_le32(vfid_event << UDMA_MB_EVENT_EN_SHIFT | token);

	mb->token_event_en = cpu_to_le32(vfid_event << HNS3_UDMA_MB_EVENT_EN_SHIFT | token);



	return udma_cmq_send(dev, desc, 1);

	return hns3_udma_cmq_send(dev, desc, 1);

}



int udma_post_mbox(struct udma_dev *dev, struct udma_cmq_desc *desc,

int hns3_udma_post_mbox(struct hns3_udma_dev *dev, struct hns3_udma_cmq_desc *desc,

			uint16_t token, int vfid_event)

{

	uint8_t status = 0;

	int ret;



	/* Waiting for the mbox to be idle */

	ret = udma_wait_mbox_complete(dev, UDMA_GO_BIT_TIMEOUT_MSECS,

				      &status);

	ret = hns3_udma_wait_mbox_complete(dev, HNS3_UDMA_GO_BIT_TIMEOUT_MSECS, &status);

	if (unlikely(ret)) {

		dev_err_ratelimited(dev->dev,

				    "failed to check post mbox status = 0x%x, ret = %d.\n",
@@ -458,7 +465,7 @@ int udma_post_mbox(struct udma_dev *dev, struct udma_cmq_desc *desc, 
	}



	/* Post new message to mbox */

	ret = __udma_post_mbox(dev, desc, token, vfid_event);

	ret = __hns3_udma_post_mbox(dev, desc, token, vfid_event);

	if (ret)

		dev_err_ratelimited(dev->dev,

				    "failed to post mailbox, ret = %d.\n", ret);
@@ -466,12 +473,12 @@ int udma_post_mbox(struct udma_dev *dev, struct udma_cmq_desc *desc, 
	return ret;

}



int udma_poll_mbox_done(struct udma_dev *dev, uint32_t timeout)

int hns3_udma_poll_mbox_done(struct hns3_udma_dev *dev, uint32_t timeout)

{

	uint8_t status = 0;

	int ret;



	ret = udma_wait_mbox_complete(dev, timeout, &status);

	ret = hns3_udma_wait_mbox_complete(dev, timeout, &status);

	if (!ret) {

		if (status != MB_ST_COMPLETE_SUCC)

			return -EBUSY;
@@ -484,22 +491,22 @@ int udma_poll_mbox_done(struct udma_dev *dev, uint32_t timeout) 
	return ret;

}



static int udma_cmd_mbox_post_hw(struct udma_dev *dev,

				 struct udma_cmq_desc *desc,

static int hns3_udma_cmd_mbox_post_hw(struct hns3_udma_dev *dev,

				      struct hns3_udma_cmq_desc *desc,

				      uint16_t token, int vfid_event)

{

	return dev->hw->post_mbox(dev, desc, token, vfid_event);

}



static int __udma_cmd_mbox_poll(struct udma_dev *dev,

				struct udma_cmq_desc *desc,

static int __hns3_udma_cmd_mbox_poll(struct hns3_udma_dev *dev,

				     struct hns3_udma_cmq_desc *desc,

				     uint32_t timeout, int vfid)

{

	int vfid_event = (vfid << 1);

	int ret, op;



	op = le32_to_cpu(((struct udma_mbox *)desc->data)->cmd_tag) & 0xff;

	ret = udma_cmd_mbox_post_hw(dev, desc, CMD_POLL_TOKEN, vfid_event);

	op = le32_to_cpu(((struct hns3_udma_mbox *)desc->data)->cmd_tag) & 0xff;

	ret = hns3_udma_cmd_mbox_post_hw(dev, desc, CMD_POLL_TOKEN, vfid_event);

	if (ret) {

		dev_err_ratelimited(dev->dev,

				    "failed to post mailbox %x in poll mode, ret = %d.\n",
@@ -510,22 +517,22 @@ static int __udma_cmd_mbox_poll(struct udma_dev *dev, 
	return dev->hw->poll_mbox_done(dev, timeout);

}



static int udma_cmd_mbox_poll(struct udma_dev *dev, struct udma_cmq_desc *desc,

static int hns3_udma_cmd_mbox_poll(struct hns3_udma_dev *dev, struct hns3_udma_cmq_desc *desc,

				   uint32_t timeout, int vfid)

{

	int ret;



	down(&dev->cmd.poll_sem);

	ret = __udma_cmd_mbox_poll(dev, desc, timeout, vfid);

	ret = __hns3_udma_cmd_mbox_poll(dev, desc, timeout, vfid);

	up(&dev->cmd.poll_sem);



	return ret;

}



void udma_cmd_event(struct udma_dev *udma_dev, uint16_t token, uint8_t status,

void hns3_udma_cmd_event(struct hns3_udma_dev *udma_dev, uint16_t token, uint8_t status,

			 uint64_t out_param)

{

	struct udma_cmd_context *ctx =

	struct hns3_udma_cmd_context *ctx =

		&udma_dev->cmd.context[token % udma_dev->cmd.max_cmds];



	if (unlikely(token != ctx->token)) {
@@ -540,14 +547,14 @@ void udma_cmd_event(struct udma_dev *udma_dev, uint16_t token, uint8_t status, 
	complete(&ctx->done);

}



static int __udma_cmd_mbox_wait(struct udma_dev *udma_dev,

				struct udma_cmq_desc *desc,

static int __hns3_udma_cmd_mbox_wait(struct hns3_udma_dev *udma_dev,

				     struct hns3_udma_cmq_desc *desc,

				     uint32_t timeout, int vfid)

{

	struct udma_cmdq *cmd = &udma_dev->cmd;

	struct hns3_udma_cmdq *cmd = &udma_dev->cmd;

	struct hns3_udma_cmd_context *context;

	int vfid_event = (vfid << 1) | 0x1;

	struct device *dev = udma_dev->dev;

	struct udma_cmd_context *context;

	int ret, op;



	spin_lock(&cmd->ctx_lock);
@@ -561,8 +568,8 @@ static int __udma_cmd_mbox_wait(struct udma_dev *udma_dev, 


	reinit_completion(&context->done);



	op = le32_to_cpu(((struct udma_mbox *)desc->data)->cmd_tag) & 0xff;

	ret = udma_cmd_mbox_post_hw(udma_dev, desc, context->token, vfid_event);

	op = le32_to_cpu(((struct hns3_udma_mbox *)desc->data)->cmd_tag) & 0xff;

	ret = hns3_udma_cmd_mbox_post_hw(udma_dev, desc, context->token, vfid_event);

	if (ret) {

		dev_err_ratelimited(dev,

				    "failed to post mailbox %x in event mode, ret = %d.\n",
@@ -588,19 +595,19 @@ static int __udma_cmd_mbox_wait(struct udma_dev *udma_dev, 
	return ret;

}



static int udma_cmd_mbox_wait(struct udma_dev *dev, struct udma_cmq_desc *desc,

static int hns3_udma_cmd_mbox_wait(struct hns3_udma_dev *dev, struct hns3_udma_cmq_desc *desc,

				   uint32_t timeout, int vfid)

{

	int ret;



	down(&dev->cmd.event_sem);

	ret = __udma_cmd_mbox_wait(dev, desc, timeout, vfid);

	ret = __hns3_udma_cmd_mbox_wait(dev, desc, timeout, vfid);

	up(&dev->cmd.event_sem);



	return ret;

}



int udma_cmd_mbox(struct udma_dev *dev, struct udma_cmq_desc *desc,

int hns3_udma_cmd_mbox(struct hns3_udma_dev *dev, struct hns3_udma_cmq_desc *desc,

		       uint32_t timeout, int vfid)

{

	bool is_busy;
@@ -610,9 +617,9 @@ int udma_cmd_mbox(struct udma_dev *dev, struct udma_cmq_desc *desc, 
			return is_busy ? -EBUSY : 0;



	if (dev->cmd.use_events)

		return udma_cmd_mbox_wait(dev, desc, timeout, vfid);

		return hns3_udma_cmd_mbox_wait(dev, desc, timeout, vfid);

	else

		return udma_cmd_mbox_poll(dev, desc, timeout, vfid);

		return hns3_udma_cmd_mbox_poll(dev, desc, timeout, vfid);

}



module_param(debug_switch, int, 0444);

drivers/ub/hw/hns3/hns3_udma_cmd.h

+95 −92

File changed.

Preview size limit exceeded, changes collapsed.

drivers/ub/hw/hns3/hns3_udma_common.h

+27 −27

File changed.

Preview size limit exceeded, changes collapsed.

drivers/ub/hw/hns3/hns3_udma_db.c

+6 −6
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/* Huawei UDMA Linux driver

/* Huawei HNS3_UDMA Linux driver

 * Copyright (c) 2023-2023 Hisilicon Limited.

 *

 * This program is free software; you can redistribute it and/or modify it
@@ -19,13 +19,13 @@ 
#include "hns3_udma_device.h"

#include "hns3_udma_db.h"



int udma_db_map_user(struct udma_ucontext *udma_ctx, uint64_t virt,

		     struct udma_db *db)

int hns3_udma_db_map_user(struct hns3_udma_ucontext *udma_ctx, uint64_t virt,

			  struct hns3_udma_db *db)

{

	struct udma_dev *udma_dev = to_udma_dev(udma_ctx->uctx.ub_dev);

	struct hns3_udma_dev *udma_dev = to_hns3_udma_dev(udma_ctx->uctx.ub_dev);

	struct hns3_udma_user_db_page *db_page;

	uint64_t page_addr = virt & PAGE_MASK;

	union ubcore_umem_flag access = {};

	struct udma_user_db_page *db_page;

	uint32_t offset;

	int ret = 0;
@@ -69,7 +69,7 @@ int udma_db_map_user(struct udma_ucontext *udma_ctx, uint64_t virt, 
	return ret;

}



void udma_db_unmap_user(struct udma_ucontext *udma_ctx, struct udma_db *db)

void hns3_udma_db_unmap_user(struct hns3_udma_ucontext *udma_ctx, struct hns3_udma_db *db)

{

	mutex_lock(&udma_ctx->pgdir_mutex);