Commit d461e96c authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull ARM SoC driver updates from Arnd Bergmann:
 "These are all the driver updates for SoC specific drivers. There are a
  couple of subsystems with individual maintainers picking up their
  patches here:

   - The reset controller subsystem add support for a few new SoC
     variants to existing drivers, along with other minor improvements

   - The OP-TEE subsystem gets a driver for the ARM FF-A transport

   - The memory controller subsystem has improvements for Tegra,
     Mediatek, Renesas, Freescale and Broadcom specific drivers.

   - The tegra cpuidle driver changes get merged through this tree this
     time. There are only minor changes, but they depend on other tegra
     driver updates here.

   - The ep93xx platform finally moves to using the drivers/clk/
     subsystem, moving the code out of arch/arm in the process. This
     depends on a small sound driver change that is included here as
     well.

   - There are some minor updates for Qualcomm and Tegra specific
     firmware drivers.

  The other driver updates are mainly for drivers/soc, which contains a
  mixture of vendor specific drivers that don't really fit elsewhere:

   - Mediatek drivers gain more support for MT8192, with new support for
     hw-mutex and mmsys routing, plus support for reset lines in the
     mmsys driver.

   - Qualcomm gains a new "sleep stats" driver, and support for the
     "Generic Packet Router" in the APR driver.

   - There is a new user interface for routing the UARTS on ASpeed BMCs,
     something that apparently nobody else has needed so far.

   - More drivers can now be built as loadable modules, in particular
     for Broadcom and Samsung platforms.

   - Lots of improvements to the TI sysc driver for better
     suspend/resume support"

  Finally, there are lots of minor cleanups and new device IDs for
  amlogic, renesas, tegra, qualcomm, mediateka, samsung, imx,
  layerscape, allwinner, broadcom, and omap"

* tag 'drivers-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (179 commits)
  optee: Fix spelling mistake "reclain" -> "reclaim"
  Revert "firmware: qcom: scm: Add support for MC boot address API"
  qcom: spm: allow compile-testing
  firmware: arm_ffa: Remove unused 'compat_version' variable
  soc: samsung: exynos-chipid: add exynosautov9 SoC support
  firmware: qcom: scm: Don't break compile test on non-ARM platforms
  soc: qcom: smp2p: Add of_node_put() before goto
  soc: qcom: apr: Add of_node_put() before return
  soc: qcom: qcom_stats: Fix client votes offset
  soc: qcom: rpmhpd: fix sm8350_mxc's peer domain
  dt-bindings: arm: cpus: Document qcom,msm8916-smp enable-method
  ARM: qcom: Add qcom,msm8916-smp enable-method identical to MSM8226
  firmware: qcom: scm: Add support for MC boot address API
  soc: qcom: spm: Add 8916 SPM register data
  dt-bindings: soc: qcom: spm: Document qcom,msm8916-saw2-v3.0-cpu
  soc: qcom: socinfo: Add PM8150C and SMB2351 models
  firmware: qcom_scm: Fix error retval in __qcom_scm_is_call_available()
  soc: aspeed: Add UART routing support
  soc: fsl: dpio: rename the enqueue descriptor variable
  soc: fsl: dpio: use an explicit NULL instead of 0
  ...
parents ae45d84f 6a035689
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+27 −0
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What:		/sys/bus/platform/drivers/aspeed-uart-routing/*/uart*
Date:		September 2021
Contact:	Oskar Senft <osk@google.com>
		Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Description:	Selects the RX source of the UARTx device.

		When read, each file shows the list of available options with currently
		selected option marked by brackets "[]". The list of available options
		depends on the selected file.

		e.g.
		cat /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1
		[io1] io2 io3 io4 uart2 uart3 uart4 io6

		In this case, UART1 gets its input from IO1 (physical serial port 1).

Users:		OpenBMC.  Proposed changes should be mailed to
		openbmc@lists.ozlabs.org

What:		/sys/bus/platform/drivers/aspeed-uart-routing/*/io*
Date:		September 2021
Contact:	Oskar Senft <osk@google.com>
		Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Description:	Selects the RX source of IOx serial port. The current selection
		will be marked by brackets "[]".
Users:		OpenBMC.  Proposed changes should be mailed to
		openbmc@lists.ozlabs.org
+5 −1
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@@ -211,6 +211,9 @@ properties:
          - qcom,gcc-msm8660
          - qcom,kpss-acc-v1
          - qcom,kpss-acc-v2
          - qcom,msm8226-smp
          # Only valid on ARM 32-bit, see above for ARM v8 64-bit
          - qcom,msm8916-smp
          - renesas,apmu
          - renesas,r9a06g032-smp
          - rockchip,rk3036-smp
@@ -297,7 +300,8 @@ properties:
      Specifies the ACC* node associated with this CPU.

      Required for systems that have an "enable-method" property
      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
      "qcom,msm8916-smp".

      * arm/msm/qcom,kpss-acc.txt

+3 −2
Original line number Diff line number Diff line
@@ -11,8 +11,9 @@ maintainers:

properties:
  compatible:
    items:
      - const: samsung,exynos4210-chipid
    enum:
      - samsung,exynos4210-chipid
      - samsung,exynos850-chipid

  reg:
    maxItems: 1
+0 −102
Original line number Diff line number Diff line
* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2

Required properties:
- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
  "jedec,lpddr2-s4"

  "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type

  "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type

  "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type

- density  : <u32> representing density in Mb (Mega bits)

- io-width : <u32> representing bus width. Possible values are 8, 16, and 32

Optional properties:

The following optional properties represent the minimum value of some AC
timing parameters of the DDR device in terms of number of clock cycles.
These values shall be obtained from the device data-sheet.
- tRRD-min-tck
- tWTR-min-tck
- tXP-min-tck
- tRTP-min-tck
- tCKE-min-tck
- tRPab-min-tck
- tRCD-min-tck
- tWR-min-tck
- tRASmin-min-tck
- tCKESR-min-tck
- tFAW-min-tck

Child nodes:
- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
  "lpddr2-timings" provides AC timing parameters of the device for
  a given speed-bin. The user may provide the timings for as many
  speed-bins as is required. Please see Documentation/devicetree/
  bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings"

Example:

elpida_ECB240ABACN : lpddr2 {
	compatible	= "Elpida,ECB240ABACN","jedec,lpddr2-s4";
	density		= <2048>;
	io-width	= <32>;

	tRPab-min-tck	= <3>;
	tRCD-min-tck	= <3>;
	tWR-min-tck	= <3>;
	tRASmin-min-tck	= <3>;
	tRRD-min-tck	= <2>;
	tWTR-min-tck	= <2>;
	tXP-min-tck	= <2>;
	tRTP-min-tck	= <2>;
	tCKE-min-tck	= <3>;
	tCKESR-min-tck	= <3>;
	tFAW-min-tck	= <8>;

	timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
		compatible	= "jedec,lpddr2-timings";
		min-freq	= <10000000>;
		max-freq	= <400000000>;
		tRPab		= <21000>;
		tRCD		= <18000>;
		tWR		= <15000>;
		tRAS-min	= <42000>;
		tRRD		= <10000>;
		tWTR		= <7500>;
		tXP		= <7500>;
		tRTP		= <7500>;
		tCKESR		= <15000>;
		tDQSCK-max	= <5500>;
		tFAW		= <50000>;
		tZQCS		= <90000>;
		tZQCL		= <360000>;
		tZQinit		= <1000000>;
		tRAS-max-ns	= <70000>;
	};

	timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
		compatible	= "jedec,lpddr2-timings";
		min-freq	= <10000000>;
		max-freq	= <200000000>;
		tRPab		= <21000>;
		tRCD		= <18000>;
		tWR		= <15000>;
		tRAS-min	= <42000>;
		tRRD		= <10000>;
		tWTR		= <10000>;
		tXP		= <7500>;
		tRTP		= <7500>;
		tCKESR		= <15000>;
		tDQSCK-max	= <5500>;
		tFAW		= <50000>;
		tZQCS		= <90000>;
		tZQCL		= <360000>;
		tZQinit		= <1000000>;
		tRAS-max-ns	= <70000>;
	};

}
+0 −1
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@@ -102,7 +102,6 @@ examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
    #include <dt-bindings/power/qcom-aoss-qmp.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    displayport-controller@ae90000 {
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