Commit d44d6c4a authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge tag 'devfreq-next-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux 

Pull devfreq changes for 5.19-rc1 from Chanwoo Choi:

"1. Update devfreq core

 - Add cpu based scaling support to passive governor. Some device like
   cache might require the dynamic frequency scaling. But, it has very
   tightly to cpu frequency. So that use passive governor to scale
   the frequency according to current cpu frequency.

  To decide the frequency of the device, the governor does one of the following:
  : Derives the optimal devfreq device opp from required-opps property of
    the parent cpu opp_table.

  : Scales the device frequency in proportion to the CPU frequency. So, if
    the CPUs are running at their max frequency, the device runs at its
    max frequency. If the CPUs are running at their min frequency, the
    device runs at its min frequency. It is interpolated for frequencies
    in between.

 2. Update devfreq drivers

  - Update rk3399_dmc.c as following:

   : Convert dt-binding document to YAML and deprecate unused properties.

   : Use Hz units for the device-tree properties of rk3399_dmc.

   : rk3399_dmc is able to set the idle time before changing the dmc clock.
     Specify idle time parameters by using nano-second unit on dt bidning.

   : Add new disable-freq properties to optimize the power-saving feature
     of rk3399_dmc.

   : Disable devfreq-event device on remove() to fix unbalanced
     enable-disable count.

   : Use devm_pm_opp_of_add_table()

   : Block PMU (Power-Management Unit) transitions when scaling frequency
     by ARM Trust Firmware in order to fix the conflict between PMU and DMC
     (Dynamic Memory Controller)."

* tag 'devfreq-next-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux:
  PM / devfreq: passive: Keep cpufreq_policy for possible cpus
  PM / devfreq: passive: Reduce duplicate code when passive_devfreq case
  PM / devfreq: Add cpu based scaling support to passive governor
  PM / devfreq: Export devfreq_get_freq_range symbol within devfreq
  PM / devfreq: rk3399_dmc: Block PMU during transitions
  soc: rockchip: power-domain: Manage resource conflicts with firmware
  PM / devfreq: rk3399_dmc: Avoid static (reused) profile
  PM / devfreq: rk3399_dmc: Use devm_pm_opp_of_add_table()
  PM / devfreq: rk3399_dmc: Disable edev on remove()
  PM / devfreq: rk3399_dmc: Support new *-ns properties
  PM / devfreq: rk3399_dmc: Support new disable-freq properties
  PM / devfreq: rk3399_dmc: Use bitfield macro definitions for ODT_PD
  PM / devfreq: rk3399_dmc: Drop excess timing properties
  PM / devfreq: rk3399_dmc: Drop undocumented ondemand DT props
  dt-bindings: devfreq: rk3399_dmc: Add more disable-freq properties
  dt-bindings: devfreq: rk3399_dmc: Specify idle params in nanoseconds
  dt-bindings: devfreq: rk3399_dmc: Fix Hz units
  dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties
  dt-bindings: devfreq: rk3399_dmc: Convert to YAML
parents 42226c98 26984d9d

Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt

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* Rockchip rk3399 DMC (Dynamic Memory Controller) device



Required properties:

- compatible:		 Must be "rockchip,rk3399-dmc".

- devfreq-events:	 Node to get DDR loading, Refer to

			 Documentation/devicetree/bindings/devfreq/event/

			 rockchip-dfi.txt

- clocks:		 Phandles for clock specified in "clock-names" property

- clock-names :		 The name of clock used by the DFI, must be

			 "pclk_ddr_mon";

- operating-points-v2:	 Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml

			 for details.

- center-supply:	 DMC supply node.

- status:		 Marks the node enabled/disabled.

- rockchip,pmu:		 Phandle to the syscon managing the "PMU general register

			 files".



Optional properties:

- interrupts:		 The CPU interrupt number. The interrupt specifier

			 format depends on the interrupt controller.

			 It should be a DCF interrupt. When DDR DVFS finishes

			 a DCF interrupt is triggered.

- rockchip,pmu:		 Phandle to the syscon managing the "PMU general register

			 files".



Following properties relate to DDR timing:



- rockchip,dram_speed_bin :	  Value reference include/dt-bindings/clock/rk3399-ddr.h,

				  it selects the DDR3 cl-trp-trcd type. It must be

				  set according to "Speed Bin" in DDR3 datasheet,

				  DO NOT use a smaller "Speed Bin" than specified

				  for the DDR3 being used.



- rockchip,pd_idle :		  Configure the PD_IDLE value. Defines the

				  power-down idle period in which memories are

				  placed into power-down mode if bus is idle

				  for PD_IDLE DFI clock cycles.



- rockchip,sr_idle :		  Configure the SR_IDLE value. Defines the

				  self-refresh idle period in which memories are

				  placed into self-refresh mode if bus is idle

				  for SR_IDLE * 1024 DFI clock cycles (DFI

				  clocks freq is half of DRAM clock), default

				  value is "0".



- rockchip,sr_mc_gate_idle :	  Defines the memory self-refresh and controller

				  clock gating idle period. Memories are placed

				  into self-refresh mode and memory controller

				  clock arg gating started if bus is idle for

				  sr_mc_gate_idle*1024 DFI clock cycles.



- rockchip,srpd_lite_idle :	  Defines the self-refresh power down idle

				  period in which memories are placed into

				  self-refresh power down mode if bus is idle

				  for srpd_lite_idle * 1024 DFI clock cycles.

				  This parameter is for LPDDR4 only.



- rockchip,standby_idle :	  Defines the standby idle period in which

				  memories are placed into self-refresh mode.

				  The controller, pi, PHY and DRAM clock will

				  be gated if bus is idle for standby_idle * DFI

				  clock cycles.



- rockchip,dram_dll_dis_freq :	  Defines the DDR3 DLL bypass frequency in MHz.

				  When DDR frequency is less than DRAM_DLL_DISB_FREQ,

				  DDR3 DLL will be bypassed. Note: if DLL was bypassed,

				  the odt will also stop working.



- rockchip,phy_dll_dis_freq :	  Defines the PHY dll bypass frequency in

				  MHz (Mega Hz). When DDR frequency is less than

				  DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.

				  Note: PHY DLL and PHY ODT are independent.



- rockchip,ddr3_odt_dis_freq :	  When the DRAM type is DDR3, this parameter defines

				  the ODT disable frequency in MHz (Mega Hz).

				  when the DDR frequency is  less then ddr3_odt_dis_freq,

				  the ODT on the DRAM side and controller side are

				  both disabled.



- rockchip,ddr3_drv :		  When the DRAM type is DDR3, this parameter defines

				  the DRAM side driver strength in ohms. Default

				  value is 40.



- rockchip,ddr3_odt :		  When the DRAM type is DDR3, this parameter defines

				  the DRAM side ODT strength in ohms. Default value

				  is 120.



- rockchip,phy_ddr3_ca_drv :	  When the DRAM type is DDR3, this parameter defines

				  the phy side CA line (incluing command line,

				  address line and clock line) driver strength.

				  Default value is 40.



- rockchip,phy_ddr3_dq_drv :	  When the DRAM type is DDR3, this parameter defines

				  the PHY side DQ line (including DQS/DQ/DM line)

				  driver strength. Default value is 40.



- rockchip,phy_ddr3_odt : 	  When the DRAM type is DDR3, this parameter defines

				  the PHY side ODT strength. Default value is 240.



- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines

				  then ODT disable frequency in MHz (Mega Hz).

				  When DDR frequency is less then ddr3_odt_dis_freq,

				  the ODT on the DRAM side and controller side are

				  both disabled.



- rockchip,lpddr3_drv :		  When the DRAM type is LPDDR3, this parameter defines

				  the DRAM side driver strength in ohms. Default

				  value is 34.



- rockchip,lpddr3_odt :		  When the DRAM type is LPDDR3, this parameter defines

				  the DRAM side ODT strength in ohms. Default value

				  is 240.



- rockchip,phy_lpddr3_ca_drv :	  When the DRAM type is LPDDR3, this parameter defines

				  the PHY side CA line (including command line,

				  address line and clock line) driver strength.

				  Default value is 40.



- rockchip,phy_lpddr3_dq_drv :	  When the DRAM type is LPDDR3, this parameter defines

				  the PHY side DQ line (including DQS/DQ/DM line)

				  driver strength. Default value is 40.



- rockchip,phy_lpddr3_odt : 	  When dram type is LPDDR3, this parameter define

				  the phy side odt strength, default value is 240.



- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter

				  defines the ODT disable frequency in

				  MHz (Mega Hz). When the DDR frequency is less then

				  ddr3_odt_dis_freq, the ODT on the DRAM side and

				  controller side are both disabled.



- rockchip,lpddr4_drv :		  When the DRAM type is LPDDR4, this parameter defines

				  the DRAM side driver strength in ohms. Default

				  value is 60.



- rockchip,lpddr4_dq_odt : 	  When the DRAM type is LPDDR4, this parameter defines

				  the DRAM side ODT on DQS/DQ line strength in ohms.

				  Default value is 40.



- rockchip,lpddr4_ca_odt :	  When the DRAM type is LPDDR4, this parameter defines

				  the DRAM side ODT on CA line strength in ohms.

				  Default value is 40.



- rockchip,phy_lpddr4_ca_drv :	  When the DRAM type is LPDDR4, this parameter defines

				  the PHY side CA line (including command address

				  line) driver strength. Default value is 40.



- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines

				  the PHY side clock line and CS line driver

				  strength. Default value is 80.



- rockchip,phy_lpddr4_dq_drv :	  When the DRAM type is LPDDR4, this parameter defines

				  the PHY side DQ line (including DQS/DQ/DM line)

				  driver strength. Default value is 80.



- rockchip,phy_lpddr4_odt :	  When the DRAM type is LPDDR4, this parameter defines

				  the PHY side ODT strength. Default value is 60.



Example:

	dmc_opp_table: dmc_opp_table {

		compatible = "operating-points-v2";



		opp00 {

			opp-hz = /bits/ 64 <300000000>;

			opp-microvolt = <900000>;

		};

		opp01 {

			opp-hz = /bits/ 64 <666000000>;

			opp-microvolt = <900000>;

		};

	};



	dmc: dmc {

		compatible = "rockchip,rk3399-dmc";

		devfreq-events = <&dfi>;

		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru SCLK_DDRC>;

		clock-names = "dmc_clk";

		operating-points-v2 = <&dmc_opp_table>;

		center-supply = <&ppvar_centerlogic>;

		upthreshold = <15>;

		downdifferential = <10>;

		rockchip,ddr3_speed_bin = <21>;

		rockchip,pd_idle = <0x40>;

		rockchip,sr_idle = <0x2>;

		rockchip,sr_mc_gate_idle = <0x3>;

		rockchip,srpd_lite_idle	= <0x4>;

		rockchip,standby_idle = <0x2000>;

		rockchip,dram_dll_dis_freq = <300>;

		rockchip,phy_dll_dis_freq = <125>;

		rockchip,auto_pd_dis_freq = <666>;

		rockchip,ddr3_odt_dis_freq = <333>;

		rockchip,ddr3_drv = <40>;

		rockchip,ddr3_odt = <120>;

		rockchip,phy_ddr3_ca_drv = <40>;

		rockchip,phy_ddr3_dq_drv = <40>;

		rockchip,phy_ddr3_odt = <240>;

		rockchip,lpddr3_odt_dis_freq = <333>;

		rockchip,lpddr3_drv = <34>;

		rockchip,lpddr3_odt = <240>;

		rockchip,phy_lpddr3_ca_drv = <40>;

		rockchip,phy_lpddr3_dq_drv = <40>;

		rockchip,phy_lpddr3_odt = <240>;

		rockchip,lpddr4_odt_dis_freq = <333>;

		rockchip,lpddr4_drv = <60>;

		rockchip,lpddr4_dq_odt = <40>;

		rockchip,lpddr4_ca_odt = <40>;

		rockchip,phy_lpddr4_ca_drv = <40>;

		rockchip,phy_lpddr4_ck_cs_drv = <80>;

		rockchip,phy_lpddr4_dq_drv = <80>;

		rockchip,phy_lpddr4_odt = <60>;

	};

Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# %YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip rk3399 DMC (Dynamic Memory Controller) device



maintainers:

  - Brian Norris <briannorris@chromium.org>



properties:

  compatible:

    enum:

      - rockchip,rk3399-dmc



  devfreq-events:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Node to get DDR loading. Refer to

      Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: dmc_clk



  operating-points-v2: true



  center-supply:

    description:

      DMC regulator supply.



  rockchip,pmu:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      Phandle to the syscon managing the "PMU general register files".



  interrupts:

    maxItems: 1

    description:

      The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS

      finishes, a DCF interrupt is triggered.



  rockchip,ddr3_speed_bin:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the

      DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3

      datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3

      being used.



  rockchip,pd_idle:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Configure the PD_IDLE value. Defines the power-down idle period in which

      memories are placed into power-down mode if bus is idle for PD_IDLE DFI

      clock cycles.

      See also rockchip,pd-idle-ns.



  rockchip,sr_idle:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Configure the SR_IDLE value. Defines the self-refresh idle period in

      which memories are placed into self-refresh mode if bus is idle for

      SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).

      See also rockchip,sr-idle-ns.

    default: 0



  rockchip,sr_mc_gate_idle:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Defines the memory self-refresh and controller clock gating idle period.

      Memories are placed into self-refresh mode and memory controller clock

      arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock

      cycles.

      See also rockchip,sr-mc-gate-idle-ns.



  rockchip,srpd_lite_idle:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Defines the self-refresh power down idle period in which memories are

      placed into self-refresh power down mode if bus is idle for

      srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4

      only.

      See also rockchip,srpd-lite-idle-ns.



  rockchip,standby_idle:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Defines the standby idle period in which memories are placed into

      self-refresh mode. The controller, pi, PHY and DRAM clock will be gated

      if bus is idle for standby_idle * DFI clock cycles.

      See also rockchip,standby-idle-ns.



  rockchip,dram_dll_dis_freq:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less

      than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.

      Note: if DLL was bypassed, the odt will also stop working.



  rockchip,phy_dll_dis_freq:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency

      is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.

      Note: PHY DLL and PHY ODT are independent.



  rockchip,auto_pd_dis_freq:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      Defines the auto PD disable frequency in MHz.



  rockchip,ddr3_odt_dis_freq:

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 1000000  # In case anyone thought this was MHz.

    description:

      When the DRAM type is DDR3, this parameter defines the ODT disable

      frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,

      the ODT on the DRAM side and controller side are both disabled.



  rockchip,ddr3_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is DDR3, this parameter defines the DRAM side drive

      strength in ohms.

    default: 40



  rockchip,ddr3_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is DDR3, this parameter defines the DRAM side ODT

      strength in ohms.

    default: 120



  rockchip,phy_ddr3_ca_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is DDR3, this parameter defines the phy side CA line

      (incluing command line, address line and clock line) drive strength.

    default: 40



  rockchip,phy_ddr3_dq_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is DDR3, this parameter defines the PHY side DQ line

      (including DQS/DQ/DM line) drive strength.

    default: 40



  rockchip,phy_ddr3_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is DDR3, this parameter defines the PHY side ODT

      strength.

    default: 240



  rockchip,lpddr3_odt_dis_freq:

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 1000000  # In case anyone thought this was MHz.

    description:

      When the DRAM type is LPDDR3, this parameter defines then ODT disable

      frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the

      ODT on the DRAM side and controller side are both disabled.



  rockchip,lpddr3_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR3, this parameter defines the DRAM side drive

      strength in ohms.

    default: 34



  rockchip,lpddr3_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT

      strength in ohms.

    default: 240



  rockchip,phy_lpddr3_ca_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR3, this parameter defines the PHY side CA line

      (including command line, address line and clock line) drive strength.

    default: 40



  rockchip,phy_lpddr3_dq_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line

      (including DQS/DQ/DM line) drive strength.

    default: 40



  rockchip,phy_lpddr3_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When dram type is LPDDR3, this parameter define the phy side odt

      strength, default value is 240.



  rockchip,lpddr4_odt_dis_freq:

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 1000000  # In case anyone thought this was MHz.

    description:

      When the DRAM type is LPDDR4, this parameter defines the ODT disable

      frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,

      the ODT on the DRAM side and controller side are both disabled.



  rockchip,lpddr4_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the DRAM side drive

      strength in ohms.

    default: 60



  rockchip,lpddr4_dq_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on

      DQS/DQ line strength in ohms.

    default: 40



  rockchip,lpddr4_ca_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on

      CA line strength in ohms.

    default: 40



  rockchip,phy_lpddr4_ca_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the PHY side CA line

      (including command address line) drive strength.

    default: 40



  rockchip,phy_lpddr4_ck_cs_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the PHY side clock

      line and CS line drive strength.

    default: 80



  rockchip,phy_lpddr4_dq_drv:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line

      (including DQS/DQ/DM line) drive strength.

    default: 80



  rockchip,phy_lpddr4_odt:

    deprecated: true

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      When the DRAM type is LPDDR4, this parameter defines the PHY side ODT

      strength.

    default: 60



  rockchip,pd-idle-ns:

    description:

      Configure the PD_IDLE value in nanoseconds. Defines the power-down idle

      period in which memories are placed into power-down mode if bus is idle

      for PD_IDLE nanoseconds.



  rockchip,sr-idle-ns:

    description:

      Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle

      period in which memories are placed into self-refresh mode if bus is idle

      for SR_IDLE nanoseconds.

    default: 0



  rockchip,sr-mc-gate-idle-ns:

    description:

      Defines the memory self-refresh and controller clock gating idle period in nanoseconds.

      Memories are placed into self-refresh mode and memory controller clock

      arg gating started if bus is idle for sr_mc_gate_idle nanoseconds.



  rockchip,srpd-lite-idle-ns:

    description:

      Defines the self-refresh power down idle period in which memories are

      placed into self-refresh power down mode if bus is idle for

      srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only.



  rockchip,standby-idle-ns:

    description:

      Defines the standby idle period in which memories are placed into

      self-refresh mode. The controller, pi, PHY and DRAM clock will be gated

      if bus is idle for standby_idle nanoseconds.



  rockchip,pd-idle-dis-freq-hz:

    description:

      Defines the power-down idle disable frequency in Hz. When the DDR

      frequency is greater than pd-idle-dis-freq, power-down idle is disabled.

      See also rockchip,pd-idle-ns.



  rockchip,sr-idle-dis-freq-hz:

    description:

      Defines the self-refresh idle disable frequency in Hz. When the DDR

      frequency is greater than sr-idle-dis-freq, self-refresh idle is

      disabled. See also rockchip,sr-idle-ns.



  rockchip,sr-mc-gate-idle-dis-freq-hz:

    description:

      Defines the self-refresh and memory-controller clock gating disable

      frequency in Hz. When the DDR frequency is greater than

      sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also

      rockchip,sr-mc-gate-idle-ns.



  rockchip,srpd-lite-idle-dis-freq-hz:

    description:

      Defines the self-refresh power down idle disable frequency in Hz. When

      the DDR frequency is greater than srpd-lite-idle-dis-freq, memory will

      not be placed into self-refresh power down mode when idle. See also

      rockchip,srpd-lite-idle-ns.



  rockchip,standby-idle-dis-freq-hz:

    description:

      Defines the standby idle disable frequency in Hz. When the DDR frequency

      is greater than standby-idle-dis-freq, standby idle is disabled. See also

      rockchip,standby-idle-ns.



required:

  - compatible

  - devfreq-events

  - clocks

  - clock-names

  - operating-points-v2

  - center-supply



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/rk3399-cru.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    memory-controller {

      compatible = "rockchip,rk3399-dmc";

      devfreq-events = <&dfi>;

      rockchip,pmu = <&pmu>;

      interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&cru SCLK_DDRC>;

      clock-names = "dmc_clk";

      operating-points-v2 = <&dmc_opp_table>;

      center-supply = <&ppvar_centerlogic>;

      rockchip,pd-idle-ns = <160>;

      rockchip,sr-idle-ns = <10240>;

      rockchip,sr-mc-gate-idle-ns = <40960>;

      rockchip,srpd-lite-idle-ns = <61440>;

      rockchip,standby-idle-ns = <81920>;

      rockchip,ddr3_odt_dis_freq = <333000000>;

      rockchip,lpddr3_odt_dis_freq = <333000000>;

      rockchip,lpddr4_odt_dis_freq = <333000000>;

      rockchip,pd-idle-dis-freq-hz = <1000000000>;

      rockchip,sr-idle-dis-freq-hz = <1000000000>;

      rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;

      rockchip,srpd-lite-idle-dis-freq-hz = <0>;

      rockchip,standby-idle-dis-freq-hz = <928000000>;

    };

drivers/devfreq/devfreq.c

+12 −8
Original line number Diff line number Diff line
@@ -112,14 +112,14 @@ static unsigned long find_available_max_freq(struct devfreq *devfreq) 
}



/**

 * get_freq_range() - Get the current freq range

 * devfreq_get_freq_range() - Get the current freq range

 * @devfreq:	the devfreq instance

 * @min_freq:	the min frequency

 * @max_freq:	the max frequency

 *

 * This takes into consideration all constraints.

 */

static void get_freq_range(struct devfreq *devfreq,

void devfreq_get_freq_range(struct devfreq *devfreq,

			    unsigned long *min_freq,

			    unsigned long *max_freq)

{
@@ -158,6 +158,7 @@ static void get_freq_range(struct devfreq *devfreq, 
	if (*min_freq > *max_freq)

		*min_freq = *max_freq;

}

EXPORT_SYMBOL(devfreq_get_freq_range);



/**

 * devfreq_get_freq_level() - Lookup freq_table for the frequency
@@ -418,7 +419,7 @@ int devfreq_update_target(struct devfreq *devfreq, unsigned long freq) 
	err = devfreq->governor->get_target_freq(devfreq, &freq);

	if (err)

		return err;

	get_freq_range(devfreq, &min_freq, &max_freq);

	devfreq_get_freq_range(devfreq, &min_freq, &max_freq);



	if (freq < min_freq) {

		freq = min_freq;
@@ -785,6 +786,7 @@ struct devfreq *devfreq_add_device(struct device *dev, 
{

	struct devfreq *devfreq;

	struct devfreq_governor *governor;

	unsigned long min_freq, max_freq;

	int err = 0;



	if (!dev || !profile || !governor_name) {
@@ -849,6 +851,8 @@ struct devfreq *devfreq_add_device(struct device *dev, 
		goto err_dev;

	}



	devfreq_get_freq_range(devfreq, &min_freq, &max_freq);



	devfreq->suspend_freq = dev_pm_opp_get_suspend_opp_freq(dev);

	devfreq->opp_table = dev_pm_opp_get_opp_table(dev);

	if (IS_ERR(devfreq->opp_table))
@@ -1587,7 +1591,7 @@ static ssize_t min_freq_show(struct device *dev, struct device_attribute *attr, 
	unsigned long min_freq, max_freq;



	mutex_lock(&df->lock);

	get_freq_range(df, &min_freq, &max_freq);

	devfreq_get_freq_range(df, &min_freq, &max_freq);

	mutex_unlock(&df->lock);



	return sprintf(buf, "%lu\n", min_freq);
@@ -1641,7 +1645,7 @@ static ssize_t max_freq_show(struct device *dev, struct device_attribute *attr, 
	unsigned long min_freq, max_freq;



	mutex_lock(&df->lock);

	get_freq_range(df, &min_freq, &max_freq);

	devfreq_get_freq_range(df, &min_freq, &max_freq);

	mutex_unlock(&df->lock);



	return sprintf(buf, "%lu\n", max_freq);
@@ -1955,7 +1959,7 @@ static int devfreq_summary_show(struct seq_file *s, void *data) 


		mutex_lock(&devfreq->lock);

		cur_freq = devfreq->previous_freq;

		get_freq_range(devfreq, &min_freq, &max_freq);

		devfreq_get_freq_range(devfreq, &min_freq, &max_freq);

		timer = devfreq->profile->timer;



		if (IS_SUPPORTED_ATTR(devfreq->governor->attrs, POLLING_INTERVAL))

drivers/devfreq/governor.h

+27 −0
Original line number Diff line number Diff line
@@ -47,6 +47,31 @@ 
#define DEVFREQ_GOV_ATTR_POLLING_INTERVAL		BIT(0)

#define DEVFREQ_GOV_ATTR_TIMER				BIT(1)



/**

 * struct devfreq_cpu_data - Hold the per-cpu data

 * @node:	list node

 * @dev:	reference to cpu device.

 * @first_cpu:	the cpumask of the first cpu of a policy.

 * @opp_table:	reference to cpu opp table.

 * @cur_freq:	the current frequency of the cpu.

 * @min_freq:	the min frequency of the cpu.

 * @max_freq:	the max frequency of the cpu.

 *

 * This structure stores the required cpu_data of a cpu.

 * This is auto-populated by the governor.

 */

struct devfreq_cpu_data {

	struct list_head node;



	struct device *dev;

	unsigned int first_cpu;



	struct opp_table *opp_table;

	unsigned int cur_freq;

	unsigned int min_freq;

	unsigned int max_freq;

};



/**

 * struct devfreq_governor - Devfreq policy governor

 * @node:		list node - contains registered devfreq governors
@@ -89,6 +114,8 @@ int devm_devfreq_add_governor(struct device *dev, 


int devfreq_update_status(struct devfreq *devfreq, unsigned long freq);

int devfreq_update_target(struct devfreq *devfreq, unsigned long freq);

void devfreq_get_freq_range(struct devfreq *devfreq, unsigned long *min_freq,

			    unsigned long *max_freq);



static inline int devfreq_update_stats(struct devfreq *df)

{

drivers/devfreq/governor_passive.c

+335 −68

File changed.

Preview size limit exceeded, changes collapsed.