Commit d41f59fd authored by Chunyan Zhang's avatar Chunyan Zhang Committed by Stephen Boyd
Browse files

clk: sprd: Add common infrastructure 



Added Spreadtrum's clock driver framework together with common
structures and interface functions.

Signed-off-by: default avatarChunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 1ded879e

drivers/clk/Kconfig

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@@ -236,6 +236,7 @@ source "drivers/clk/mvebu/Kconfig" 
source "drivers/clk/qcom/Kconfig"

source "drivers/clk/renesas/Kconfig"

source "drivers/clk/samsung/Kconfig"

source "drivers/clk/sprd/Kconfig"

source "drivers/clk/sunxi-ng/Kconfig"

source "drivers/clk/tegra/Kconfig"

source "drivers/clk/ti/Kconfig"

drivers/clk/Makefile

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@@ -85,6 +85,7 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ 
obj-$(CONFIG_ARCH_SIRF)			+= sirf/

obj-$(CONFIG_ARCH_SOCFPGA)		+= socfpga/

obj-$(CONFIG_PLAT_SPEAR)		+= spear/

obj-$(CONFIG_ARCH_SPRD)			+= sprd/

obj-$(CONFIG_ARCH_STI)			+= st/

obj-$(CONFIG_ARCH_SUNXI)		+= sunxi/

obj-$(CONFIG_ARCH_SUNXI)		+= sunxi-ng/

drivers/clk/sprd/Kconfig

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config SPRD_COMMON_CLK

	tristate "Clock support for Spreadtrum SoCs"

	depends on ARCH_SPRD || COMPILE_TEST

	default ARCH_SPRD

drivers/clk/sprd/Makefile

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obj-$(CONFIG_SPRD_COMMON_CLK)	+= clk-sprd.o



clk-sprd-y	+= common.o

drivers/clk/sprd/common.c

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// SPDX-License-Identifier: GPL-2.0

//

// Spreadtrum clock infrastructure

//

// Copyright (C) 2017 Spreadtrum, Inc.

// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>



#include <linux/mfd/syscon.h>

#include <linux/module.h>

#include <linux/of_address.h>

#include <linux/of_platform.h>

#include <linux/regmap.h>



#include "common.h"



static const struct regmap_config sprdclk_regmap_config = {

	.reg_bits	= 32,

	.reg_stride	= 4,

	.val_bits	= 32,

	.max_register	= 0xffff,

	.fast_io	= true,

};



static void sprd_clk_set_regmap(const struct sprd_clk_desc *desc,

			 struct regmap *regmap)

{

	int i;

	struct sprd_clk_common *cclk;



	for (i = 0; i < desc->num_clk_clks; i++) {

		cclk = desc->clk_clks[i];

		if (!cclk)

			continue;



		cclk->regmap = regmap;

	}

}



int sprd_clk_regmap_init(struct platform_device *pdev,

			 const struct sprd_clk_desc *desc)

{

	void __iomem *base;

	struct device_node *node = pdev->dev.of_node;

	struct regmap *regmap;



	if (of_find_property(node, "sprd,syscon", NULL)) {

		regmap = syscon_regmap_lookup_by_phandle(node, "sprd,syscon");

		if (IS_ERR_OR_NULL(regmap)) {

			pr_err("%s: failed to get syscon regmap\n", __func__);

			return PTR_ERR(regmap);

		}

	} else {

		base = of_iomap(node, 0);

		regmap = devm_regmap_init_mmio(&pdev->dev, base,

					       &sprdclk_regmap_config);

		if (IS_ERR_OR_NULL(regmap)) {

			pr_err("failed to init regmap\n");

			return PTR_ERR(regmap);

		}

	}



	sprd_clk_set_regmap(desc, regmap);



	return 0;

}

EXPORT_SYMBOL_GPL(sprd_clk_regmap_init);



int sprd_clk_probe(struct device *dev, struct clk_hw_onecell_data *clkhw)

{

	int i, ret;

	struct clk_hw *hw;



	for (i = 0; i < clkhw->num; i++) {



		hw = clkhw->hws[i];



		if (!hw)

			continue;



		ret = devm_clk_hw_register(dev, hw);

		if (ret) {

			dev_err(dev, "Couldn't register clock %d - %s\n",

				i, hw->init->name);

			return ret;

		}

	}



	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clkhw);

	if (ret)

		dev_err(dev, "Failed to add clock provider\n");



	return ret;

}

EXPORT_SYMBOL_GPL(sprd_clk_probe);



MODULE_LICENSE("GPL v2");