Commit d3f23ab9 authored by Andrzej Hajda's avatar Andrzej Hajda
Browse files

drm/i915: use direct alias for i915 in requests 



i915_request contains direct alias to i915, there is no point to go via
rq->engine->i915.

v2: added missing rq.i915 initialization in measure_breadcrumb_dw.

Signed-off-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: default avatarNirmoy Das <nirmoy.das@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230720113002.1541572-1-andrzej.hajda@intel.com
parent e4731b51

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

+2 −2
Original line number Diff line number Diff line
@@ -2230,8 +2230,8 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq) 
	u32 *cs;

	int i;



	if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {

		drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");

	if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) {

		drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n");

		return -EINVAL;

	}

drivers/gpu/drm/i915/gt/gen2_engine_cs.c

+1 −1
Original line number Diff line number Diff line
@@ -76,7 +76,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode) 
	cmd = MI_FLUSH;

	if (mode & EMIT_INVALIDATE) {

		cmd |= MI_EXE_FLUSH;

		if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)

		if (IS_G4X(rq->i915) || GRAPHICS_VER(rq->i915) == 5)

			cmd |= MI_INVALIDATE_ISP;

	}

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+9 −9
Original line number Diff line number Diff line
@@ -39,11 +39,11 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode) 
		 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL

		 * pipe control.

		 */

		if (GRAPHICS_VER(rq->engine->i915) == 9)

		if (GRAPHICS_VER(rq->i915) == 9)

			vf_flush_wa = true;



		/* WaForGAMHang:kbl */

		if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))

		if (IS_KBL_GRAPHICS_STEP(rq->i915, 0, STEP_C0))

			dc_flush_wa = true;

	}
@@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv 
static int mtl_dummy_pipe_control(struct i915_request *rq)

{

	/* Wa_14016712196 */

	if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||

	    IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {

	if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||

	    IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {

		u32 *cs;



		/* dummy PIPE_CONTROL + depth flush */
@@ -267,7 +267,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) 
		else if (engine->class == COMPUTE_CLASS)

			flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;



		if (!HAS_FLAT_CCS(rq->engine->i915))

		if (!HAS_FLAT_CCS(rq->i915))

			count = 8 + 4;

		else

			count = 8;
@@ -285,7 +285,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) 


		cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);



		if (!HAS_FLAT_CCS(rq->engine->i915)) {

		if (!HAS_FLAT_CCS(rq->i915)) {

			/* hsdes: 1809175790 */

			cs = gen12_emit_aux_table_inv(rq->engine->gt,

						      cs, GEN12_GFX_CCS_AUX_NV);
@@ -307,7 +307,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) 
	if (mode & EMIT_INVALIDATE) {

		cmd += 2;



		if (!HAS_FLAT_CCS(rq->engine->i915) &&

		if (!HAS_FLAT_CCS(rq->i915) &&

		    (rq->engine->class == VIDEO_DECODE_CLASS ||

		     rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {

			aux_inv = rq->engine->mask &
@@ -754,7 +754,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs) 


u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)

{

	struct drm_i915_private *i915 = rq->engine->i915;

	struct drm_i915_private *i915 = rq->i915;

	u32 flags = (PIPE_CONTROL_CS_STALL |

		     PIPE_CONTROL_TLB_INVALIDATE |

		     PIPE_CONTROL_TILE_CACHE_FLUSH |
@@ -775,7 +775,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) 
		/* Wa_1409600907 */

		flags |= PIPE_CONTROL_DEPTH_STALL;



	if (!HAS_3D_PIPELINE(rq->engine->i915))

	if (!HAS_3D_PIPELINE(rq->i915))

		flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;

	else if (rq->engine->class == COMPUTE_CLASS)

		flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+1 −0
Original line number Diff line number Diff line
@@ -1333,6 +1333,7 @@ static int measure_breadcrumb_dw(struct intel_context *ce) 
	if (!frame)

		return -ENOMEM;



	frame->rq.i915 = engine->i915;

	frame->rq.engine = engine;

	frame->rq.context = ce;

	rcu_assign_pointer(frame->rq.timeline, ce->timeline);

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

+1 −1
Original line number Diff line number Diff line
@@ -2717,7 +2717,7 @@ static int emit_pdps(struct i915_request *rq) 
	int err, i;

	u32 *cs;



	GEM_BUG_ON(intel_vgpu_active(rq->engine->i915));

	GEM_BUG_ON(intel_vgpu_active(rq->i915));



	/*

	 * Beware ye of the dragons, this sequence is magic!