Unverified Commit d3d549aa authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!530 Backport CVEs and bugfixes 

Merge Pull Request from: @zhangjialin11 
 
Pull new CVEs:
CVE-2023-1281
CVE-2022-48423
CVE-2023-1249
CVE-2022-48425
CVE-2022-48424
CVE-2023-28327
CVE-2023-28466
CVE-2023-1380

block and md/raid6 bugfixes from Zhong Jinghua
fs bugfixes from Zhihao Cheng and Baokun Li
tty bugfix from Yi Yang
mm bugfixes from ZhangPeng and Ze Zuo
bpf bugfixes from Pu Lehui and Liu Jian
ima bugfix from GUO Zihua
softirq and arch bugfixes from Lin Yujun 
 
Link:https://gitee.com/openeuler/kernel/pulls/530

 

Reviewed-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents 7d5eb691 8b9119c1

Documentation/arm64/silicon-errata.rst

+4 −0
Original line number Diff line number Diff line
@@ -76,10 +76,14 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A57      | #1319537        | ARM64_ERRATUM_1319367       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A57      | #1742098        | ARM64_ERRATUM_1742098       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A72      | #853709         | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A72      | #1319367        | ARM64_ERRATUM_1319367       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A72      | #1655431        | ARM64_ERRATUM_1742098       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1188873,1418040| ARM64_ERRATUM_1418040       |

arch/arm/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -1023,6 +1023,17 @@ config ARM_ERRATA_764369 
	  relevant cache maintenance functions and sets a specific bit

	  in the diagnostic control register of the SCU.



config ARM_ERRATA_764319

	bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"

	depends on CPU_V7

	help

	  This option enables the workaround for the 764319 Cortex A-9 erratum.

	  CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an

	  unexpected Undefined Instruction exception when the DBGSWENABLE

	  external pin is set to 0, even when the CP14 accesses are performed

	  from a privileged mode. This work around catches the exception in a

	  way the kernel does not stop execution.



config ARM_ERRATA_775420

       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"

       depends on CPU_V7

arch/arm/kernel/hw_breakpoint.c

+26 −0
Original line number Diff line number Diff line
@@ -941,6 +941,23 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, 
	return ret;

}



#ifdef CONFIG_ARM_ERRATA_764319

static int oslsr_fault;



static int debug_oslsr_trap(struct pt_regs *regs, unsigned int instr)

{

	oslsr_fault = 1;

	instruction_pointer(regs) += 4;

	return 0;

}



static struct undef_hook debug_oslsr_hook = {

	.instr_mask  = 0xffffffff,

	.instr_val = 0xee115e91,

	.fn = debug_oslsr_trap,

};

#endif



/*

 * One-time initialisation.

 */
@@ -974,7 +991,16 @@ static bool core_has_os_save_restore(void) 
	case ARM_DEBUG_ARCH_V7_1:

		return true;

	case ARM_DEBUG_ARCH_V7_ECP14:

#ifdef CONFIG_ARM_ERRATA_764319

		oslsr_fault = 0;

		register_undef_hook(&debug_oslsr_hook);

		ARM_DBG_READ(c1, c1, 4, oslsr);

		unregister_undef_hook(&debug_oslsr_hook);

		if (oslsr_fault)

			return false;

#else

		ARM_DBG_READ(c1, c1, 4, oslsr);

#endif

		if (oslsr & ARM_OSLSR_OSLM0)

			return true;

		fallthrough;

arch/arm64/Kconfig

+16 −0
Original line number Diff line number Diff line
@@ -497,6 +497,22 @@ config ARM64_ERRATUM_834220 


	  If unsure, say Y.



config ARM64_ERRATUM_1742098

    bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic     instructions in a sequence"

    depends on COMPAT

    default y

    help

      This option removes the AES hwcap for aarch32 user-space to

      workaround erratum 1742098 on Cortex-A57 and Cortex-A72.



      Affected parts may corrupt the AES state if an interrupt is

      taken between a pair of AES instructions. These instructions

      are only present if the cryptography extensions are present.

      All software should have a fallback implementation for CPUs

      that don't implement the cryptography extensions.

 

      If unsure, say Y.



config ARM64_ERRATUM_845719

	bool "Cortex-A53: 845719: a load might read incorrect data"

	depends on AARCH32_EL0

arch/arm64/include/asm/cpucaps.h

+1 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ 
#define ARM64_HAS_ECV				64

#define ARM64_HAS_EPAN				65

#define ARM64_SPECTRE_BHB			66

#define ARM64_WORKAROUND_1742098	67



#define ARM64_NCAPS				80